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latticeecp/ec family data sheet
www.latticesemi.com 1-1 introduction_01 j une 2004 advance data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. features ? 1.5k to 41k lut4s ? 65 to 576 i/os ? density migration supported ? high performance multiply and accumulate ?4 to 10 blocks ? 4 to 10 36x36 multipliers or ? 16 to 40 18x18 multipliers or ? 32 to 80 9x9 multipliers ? 18 kbits to 645 kbits sysmem? embedded block ram (ebr) ? up to 163 kbits distributed ram ? flexible memory resources: ? distributed and block memory ? programmable sysio? buffer supports wide r ange of interfaces: ? l vcmos 3.3/2.5/1.8/1.5/1.2 ? l vttl ? sstl 3/2 class i, ii, sstl18 class i ? hstl 18 class i, ii, iii, hstl15 class i, iii ? pci ? l vds, bus-lvds, lvpecl ? implements interface up to ddr333 (166mhz) ? up to 4 analog plls per device ? clock multiply, divide and phase shifting ? ieee standard 1149.1 boundary scan, plus isptracy? internal logic analyzer capability ? spi boot ash interface ? 1.2v power supply ?f eatures optimized for mainstream applications ?l ow cost tqfp and pqfp packaging ta b le 1-1. latticeecp/ec family selection guide device lfec1 lfec3 lfec6/ lfecp6 lfec10/ lfecp10 lfec15/ lfecp15 lfec20/ lfecp20 lfec40/ lfecp40 pfu/pff rows 12 16 24 32 40 44 64 pfu/pff columns 16 24 32 40 48 56 80 pfus/pffs 192 384 768 1280 1920 2464 5120 luts (k) 1.5 3.1 6.1 10.2 15.4 19.7 41.0 distributed ram (kbits) 6 12 25 41 61 79 164 ebr sram (kbits) 18 55 92 277 350 424 645 ebr sram blocks 2 6 10 30 38 46 70 sysdsp blocks 1 ?? 456710 18x18 multipliers 1 ??16 20 24 28 40 v cc v oltage (v) 1.2 1.2 1.2 1.2 1.2 1.2 1.2 number of plls 2224444 pa ck ag es and i/o combinations: 100-pin tqfp (14 x 14 mm) 67 67 144-pin tqfp (20 x 20 mm) 97 97 97 208-pin pqfp (28 x 28 mm) 112 145 147 147 256-ball fpbga (17 x 17 mm) 160 195 195 195 484-ball fpbga (23 x 23 mm) 224 288 352 360 672-ball fpbga (27 x 27 mm) 400 496 900-ball fpbga (31 x 31 mm) 576 1. latticeecp devices only. latticeecp/ec family data sheet introduction
1-2 introduction lattice semiconductor latticeecp/ec family data sheet introduction the latticeecp/ec family of fpga devices has been optimized to deliver mainstream fpga features at low cost. f or maximum performance and value, the latticeecp (ec onomy p lus) fpga concept combines an ef cient fpga f abric with high-speed dedicated functions. lattice?s rst family to implement this approach is the latticeecp-dsp (ec onomy p lus dsp ) family, providing dedicated high-performance dsp blocks on-chip. the latticeec? (ec on- omy) family supports all the general purpose features of latticeecp devices without dedicated function blocks to achieve lower cost solutions. the lattice-ecp/ec fpga fabric, which was designed from the outset with low cost in mind, contains all the criti- cal fpga elements: lut-based logic, distributed and embedded memory, plls and support for mainstream i/os. dedicated ddr memory interface logic is also included to support this memory that is becoming increasingly prev- alent in cost-sensitive applications. the isplever ? design tool from lattice allows large complex designs to be ef ciently implemented using the latti- ceecp/ec family of fpga devices. synthesis library support for latticeecp/ec is available for popular logic syn- thesis tools. the isplever tool uses the synthesis tool output along with the constraints from its oor planning tools to place and route the design in the latticeecp/ec device. the isplever tool extracts the timing from the routing and back-annotates it into the design for timing veri cation. lattice provides many pre-designed ip (intellectual property) isplevercore? modules for the latticeecp/ec f amily. by using these ips as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
www.latticesemi.com 2-1 architecture_01 j une 2004 advance data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. architecture overview the latticeecp?-dsp and latticeec? architectures contain an array of logic blocks surrounded by programma- b le i/o cells (pic). interspersed between the rows of logic blocks are rows of sysmem embedded block ram (ebr) as shown in figures 2-1 and 2-2. in addition, latticeecp-dsp supports an additional row of dsp blocks as shown in figure 2-2. there are two kinds of logic blocks, the programmable functional unit (pfu) and programmable functional unit without ram/rom (pff). the pfu contains the building blocks for logic, arithmetic, ram, rom and register func- tions. the pff block contains building blocks for logic, arithmetic and rom functions. both pfu and pff blocks are optimized for e xibility allowing complex designs to be implemented quickly and ef ciently. logic blocks are arranged in a two-dimensional array. only one type of block is used per row. the pfu blocks are used on the out- side rows. the rest of the core consists of rows of pff blocks interspersed with rows of pfu blocks. for every three rows of pff blocks there is a row of pfu blocks. each pic block encompasses two pios (pio pairs) with their respective sysio interfaces. pio pairs on the left and r ight edges of the device can be con gured as lvds transmit/receive pairs. sysmem ebrs are large dedicated fast memory blocks. they can be con gured as ram or rom. the pfu, pff, pic and ebr blocks are arranged in a two-dimensional grid with rows and columns as shown in figure 2-1. the blocks are connected with many vertical and horizontal routing channel resources. the place and route software tool automatically allocates these routing resources. at the end of the rows containing the sysmem blocks are the sysclock phase locked loop (pll) blocks. these plls have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. the latticeecp/ec architecture provides up to four plls per device. every device in the family has a jtag port with internal logic analyzer (isptracy) capability. the sysconfig? port which allows for serial or parallel device con guration. the latticeecp/ec devices use 1.2v as their core volt- age. latticeecp/ec family data sheet architecture
2-2 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-1. simpli?d block diagram, latticeecp/ec device (top level) figure 2-2. simpli?d block diagram, latticeecp-dsp device (top level) programmable i/o cell (pic) includes sysio interface sysconfig programming po rt (includes dedicated and dual use pins) programmable functional unit (pfu) sysclock pll pff (pfu without ram) jtag port sysmem embedded block ram (ebr) programmable i/o cell (pic) includes sysio interface sysconfig programming po rt (includes dedicated and dual use pins) programmable functional unit (pfu) sysdsp block sysclock pll pff (fast pfu without ram/rom) jtag port sysmem embedded block ram (ebr)
2-3 architecture lattice semiconductor latticeecp/ec family data sheet pfu and pff blocks the core of the latticeecp/ec devices consists of pfu and pff blocks. the pfus can be programmed to perform logic, arithmetic, distributed ram and distributed rom functions. pff blocks can be programmed to perform logic, arithmetic and rom functions. except where necessary, the remainder of the data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices, numbered 0-3 as shown in figure 2-3. all the interconnec- tions to and from pfu blocks are from routing. there are 53 inputs and 25 outputs associated with each pfu block. figure 2-3. pfu diagram slice each slice contains two lut4 lookup tables feeding two registers (programmed to be in ff or latch mode), and some associated logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider ram/rom functions. figure 2-4 shows an overview of the internal logic of the slice. the registers in the slice can be con gured for positive/negative and edge/level clocks. there are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or pfu). there are 7 outputs: 6 to routing and one to carry-chain (to adjacent pfu). table 2-1 lists the signals associated with each slice. slice 0 lut4 & carry lut4 & carry ff/ latch d ff/ latch d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 & carry lut4 & carry ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d
2-4 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-4. slice diagram ta b le 2-1. slice signal descriptions function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0 multipurpose input input multi-purpose m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fcin fast carry in 1 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco for the right most pfu the fast carry chain output 1 1. see figure 2-3 for connection details. 2. requires two pfus. lut4 & carry lut4 & carry slice a0 b0 c0 d0 ff/ latch ofx0 f0 q0 a1 b1 c1 d1 ci ci co co f sum ce clk lsr ff/ latch ofx1 f1 q1 f sum d d m1 to / from different slice / pfu to / from different slice / pfu lut expansion mux m0 ofx0 from routing to routing control signals selected and inverted per slice in routing interslice signals are not shown
2-5 architecture lattice semiconductor latticeecp/ec family data sheet modes of operation each slice is capable of four modes of operation: logic, ripple, ram and rom. the slice in the pff is capable of all modes except ram. table 2-2 lists the modes and the capability of the slice blocks. ta b le 2-2. slice modes logic mode: in this mode, the luts in each slice are con gured as 4-input combinatorial lookup tables. a lut4 can have 16 possible input combinations. any logic function with four inputs can be generated by programming this lookup table. since there are two lut4s per slice, a lut5 can be constructed within one slice. larger lookup tables such as lut6, lut7 and lut8 can be constructed by concatenating other slices. ripple mode: ripple mode allows the ef cient implementation of small arithmetic functions. in ripple mode, the fol- lowing functions can be implemented by each slice: ? addition 2-bit ? subtraction 2-bit ? add/subtract 2-bit using dynamic control ? up counter 2-bit ?d o wn counter 2-bit ? ripple mode multiplier building block ? comparator functions of a and b inputs -a greater-than-or-equal-to b -a not-equal-to b -a less-than-or-equal-to b tw o additional signals: carry generate and carry propagate are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices. ram mode: in this mode, distributed ram can be constructed using each lut block as a 16x1-bit memory. through the combination of luts and slices, a variety of different memories can be constructed. the lattice design tools support the creation of a variety of different size memories. where appropriate, the soft- w are will construct these using distributed memory primitives that represent the capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. figure 2-5 shows the dis- tributed memory primitive block diagrams. dual port memories involve the pairing of two slices, one slice functions as the read-write port. the other companion slice supports the read-only port. for more information on using ram in latticeecp/ec devices, please see details of additional technical documentation at the end of this data sheet. ta b le 2-3. number of slices required for implementing distributed ram logic ripple ram rom pfu slice lut 4x2 or lut 5x1 2-bit arithmetic unit spr16x2 rom16x1 x 2 pff slice lut 4x2 or lut 5x1 2-bit arithmetic unit n/a rom16x1 x 2 spr16x2 dpr16x2 number of slices 1 2 note: spr = single port ram, dpr = dual port ram
2-6 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-5. distributed memory primatives r om mode: the rom mode uses the same principal as the ram modes, but without the write port. pre-loading is accomplished through the programming interface during con guration. pfu modes of operation slices can be combined within a pfu to form larger functions. table 2-4 tabulates these modes and documents the functionality possible at the pfu level. ta b le 2-4. pfu modes of operation routing there are many resources provided in the latticeecp/ec devices to route signals individually or as busses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. logic ripple ram 1 rom lut 4x8 or mux 2x1 x 8 2-bit add x 4 spr16x2 x 4 dpr16x2 x 2 r om16x1 x 8 lut 5x4 or mux 4x1 x 4 2-bit sub x 4 spr16x4 x 2 dpr16x4 x 1 r om16x2 x 4 lut 6x 2 or mux 8x1 x 2 2-bit counter x 4 spr16x8 x 1 rom16x4 x 2 lut 7x1 or mux 16x1 x 1 2-bit comp x 4 rom16x8 x 1 1. these modes are not available in pff blocks do1 do0 di0 di1 ad0 ad1 ad2 ad3 wre ck do0 ad0 ad1 ad2 ad3 dpr16x2 spr16x2 r om16x1 rdo1 rdo0 di0 di1 wck wre wdo1 wdo0 wad0 w ad1 wad2 wad3 rad0 rad1 rad2 rad3
2-7 architecture lattice semiconductor latticeecp/ec family data sheet the inter-pfu connections are made with x1 (spans two pfu), x2 (spans three pfu) and x6 (spans seven pfu). the x1 and x2 connections provide fast and ef cient connections in horizontal and vertical directions. the x2 and x6 resources are buffered allowing both short and long connections routing between pfus. the isplever design tool takes the output of the synthesis tool and places and routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. clock distribution network the clock inputs are selected from external i/o, the sysclock? plls or routing. these clock inputs are fed through the chip via a clock distribution system. primary clock sources latticeecp/ec devices derive clocks from three primary sources: pll outputs, dedicated clock inputs and routing. latticeecp/ec devices have two to four sysclock plls, located on the left and right sides of the device. there are four dedicated clock inputs, one on each side of the device. figure 2-6 shows the 20 primary clock sources. figure 2-6. clock sources clock routing the clock routing structure in latticeecp/ec devices consists of four primary clock lines and a secondary clock network per quadrant. the primary clocks are generated from muxs located in each quadrant. figure 2-7 shows this clock routing. the primary clock lines also feed into a secondary clock network (not shown). the secondary clock branches are tapped at every pfu. these secondary clock networks can also be used for controls and high f an out data. each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in figure 2-8. fr om routing clock input from routing pll input clock input pll input pll input clock input pll input fr om routing clock input from routing pll pll pll pll 20 primary clock sources to quadrant clock selection note: smaller devices have two plls.
2-8 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-7. per quadrant clock selection figure 2-8. slice clock selection sysclock phase locked loops (plls) the pll clock input, from pin or routing, feeds into an input clock divider. there are four sources of feedback signal to the feedback divider: from the clock net, from output of the post scalar divider, from the routing or from an exter- nal pin. there is a pll_lock signal to indicate that vco has locked on to the input clock signal. figure 2-9 shows the sysclock pll diagram. the setup and hold times of the device can be improved by programming a delay in the feedback or input path of the pll which will advance or delay the output clock with reference to the input clock. this delay can be either pro- gr ammed during con guration or can be adjusted dynamically. in dynamic mode, the pll may lose lock after adjustment and not relock until the t lock parameter has been satis ed. additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the clkos output. the sysclock plls provide the ability to synthesize clock frequencies. each pll has four dividers associated with it: input clock divider, feedback divider, port scalar divider and secondary clock divider. the input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. the post scalar divider allows the vco to operate at higher frequencies than the clock output, thereby increasing the fre- quency range. the secondary divider is used to derive lower frequency outputs. 4 primary clocks (clk0, clk1, clk2, clk3) per quadrant 20 primary clock sources: 12 plls + 4 pios + 4 routing 1 1. smaller devices have fewer pll related lines. primary clock secondary clock routing clock to slice gnd 4 3
2-9 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-9. pll diagram figure 2-10 shows the available macros for the pll. table 2-5 provides signal description of the pll block. figure 2-10. pll primitive ta b le 2-5. pll signal descriptions signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from pll output, clocknet, routing or external pin rst i ?1? to reset input clock divider clkos o pll output clock to clock tree (phase shifted/duty cycle changed) clkop o pll output clock to clock tree (no phase shift) clkok o pll output to clock tree through secondary clock divider lock o ?1? indicates pll lock to clki ddamode i dynamic delay enable. ?1? pin control (dynamic), ?0?: fuse control (static) ddaizr i dynamic delay zero. ?1?: delay = 0, ?0?: delay = on ddailag i dynamic delay lag/lead. ?1?: lag, ?0?: lead ddaidel[2:0] i dynamic delay input ddaozr o dynamic delay zero output ddaolag o dynamic delay lag/lead output ddaodel[2:0] o dynamic delay output vco clkos clkok lock rst clkfb (from post scalar divider output, clock net or e xternal pin dynamic delay adjustment input clock divider (clki) feedback divider (clkfb) po st scalar divider (clkop) phase/duty select secondary clock divider (clkok) delay adjust v oltage controlled oscillator clki (from routing or e xternal pin) clkop epllb clkop clki clkfb lock ehxpllb clkos clki clkfb clkok lock rst clkop ddaizr ddailag dda mode ddaidel[2:0] ddaozr ddaolag ddaodel[2:0]
2-10 architecture lattice semiconductor latticeecp/ec family data sheet f or more information on the pll, please see details of additional technical documentation at the end of this data sheet. sysmem memory the latticeecp/ec family of devices contain a number of sysmem embedded block ram (ebr). the ebr con- sists of a 9-kbit ram, with dedicated input and output registers. sysmem memory block the sysmem block can implement single port, dual port or pseudo dual port memories. each block can be used in a variety of depths and widths as shown in table 2-6. ta b le 2-6. sysmem block con?urations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb w ord 0 to msb word 0, lsb word 1 to msb word 1 and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded during device con guration. by preloading the ram block during the chip con guration cycle and disabling the write controls, the sysmem block can also be utilized as a r om. memory cascading larger and deeper blocks of rams can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, based on speci c design inputs. single, dual and pseudo-dual port modes figure 2-11 shows the four basic memory con gurations and their input/output names. in all the sysmem ram modes the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. memory mode con gurations single port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 tr ue dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 pseudo dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36
2-11 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-11. sysmem ebr primitives the ebr memory supports three forms of write behavior for single port or dual port operation: 1. normal ? data on the output appears only during read cycle. during a write cycle, the data (at the current address) does not appear on the output. 2. write through ? a copy of the input data appears at the output of the same port, during a write cycle. 3. read-before-write ? when new data is being written, the old content of the address appears at the output. memory core reset the memory array in the ebr utilizes latches at the a and b output ports. these latches can be reset asynchro- nously or synchronously. rsta and rstb are local signals, which reset the output latches associated with port a and port b respectively. the global reset (gsrn) signal resets both ports. the output data latches and associated resets for both ports are as shown in figure 2-12. ebr ad[12:0] di[35:0] clk ce rst we cs[2:0] do[35:0] single port ram ebr t rue dual port ram pseudo-dual port ram rom ad[12:0] clk ce do[35:0] rst cs[2:0] ebr ebr ada[12:0] dia[17:0] clka cea rsta wea csa[2:0] doa[17:0] adb[12:0] dib[17:0] clkb ceb rstb web csb[2:0] dob[17:0] adw[12:0] di[35:0] clkw cew adr[12:0] do[35:0] cer clkr we rst cs[2:0]
2-12 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-12. memory core reset f or further information on sysmem ebr block, please see the details of additional technical documentation at the end of this data sheet. sysdsp block the latticeecp-dsp family provides a sysdsp block making it ideally suited for low cost, high performance digital signal processing (dsp) applications. typical functions used in these applications are finite impulse response (fir) lters; fast fourier transforms (fft) functions, correlators, reed-solomon/turbo/convolution encoders and decoders. these complex signal processing functions use similar building blocks such as multiply-adders and mul- tiply-accumulators. sysdsp block approach compare to general dsp conventional general-purpose dsp chips typically contain one to four (multiply and accumulate) mac units with x ed data-width multipliers; this leads to limited parallelism and limited throughput. their throughput is increased by higher clock speeds. the latticeecp, on the other hand, has many dsp blocks that support different data-widths. this allows the designer to use highly parallel implementations of dsp functions. the designer can optimize the dsp performance vs. area by choosing appropriate level of parallelism. figure 2-13 compares the serial and the parallel implementations. q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn programmable disable rsta l clr
2-13 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-13. comparison of general dsp and latticeecp-dsp approaches sysdsp block capabilities the sysdsp block in the latticeecp-dsp family supports four functional elements in three 9, 18 and 36 data path widths. the user selects a function element for a dsp block and then selects the width and type (signed/unsigned) of its operands. the operands in the latticeecp-dsp family sysdsp blocks can be either signed or unsigned but not mixed within a function element. similarly, the operand widths cannot be mixed within a block. the resources in each sysdsp block can be con gured to support the following four elements: ? mult (multiply) ?m ac (multiply, accumulate) ? multadd (multiply, addition/subtraction) ? multaddsum (multiply, addition/subtraction, accumulate) the number of elements available in each block depends in the width selected from the three available options x9, x18, and x36. a number of these elements are concatenated for highly parallel implementations of dsp functions. ta b le 2-1 shows the capabilities of the block. ta b le 2-7. maximum number of elements in a block some options are available in four elements. the input register in all the elements can be directly loaded or can be loaded as shift register from previous operand registers. in addition by selecting ?dynamic operation? in the ?signed/ unsigned? options the operands can be switched between signed and unsigned on every cycle. similarly by select- ing ?dynamic operation? in the ?add/sub? option the accumulator can be switched between addition and subtraction on every cycle. width of multiply x9 x18 x36 mult 8 4 1 mac 2 1 ? multadd 4 2 ? multaddsum 4 2 ? multiplier 0 operand a operand b operand a operand b operand a operand b multiplier 1 multiplier (k-1) accumulator output m/k loops single multiplier x xx x operand a accumulator operand b m loops function implemented in general purpose dsp function implemented in latticeecp
2-14 architecture lattice semiconductor latticeecp/ec family data sheet mult sysdsp element this multiplier element implements a multiply with no addition or accumulator nodes. the two operands, a and b, are multiplied and the result is available at the output. the user can enable the input/output and pipeline registers. figure 2-14 shows the mult sysdsp element. figure 2-14. mult sysdsp element mac sysdsp element in this case the two operands, a and b, are multiplied and the result is added with the previous accumulated value. this accumulated value is available at the output. the user can enable the input and pipeline registers but the out- put register is always enabled. the output register is used to store the accumulated value. a registered over ow signal is also available. the over ow conditions are provided later in this document. figure 2-15 shows the mac sysdsp element. multiplier x n m m n m n m n n m m+n m+n (default) pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) pipeline register input register multiplier multiplicand signed shift register a in shift register b in shift register a out shift register b out output input data register a input data register b output register to multiplier
2-15 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-15. mac sysdsp element multadd sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and a2. the user can enable the input, output and pipeline registers. figure 2-16 shows the multadd sysdsp element. figure 2-16. multadd multiplier x n m m+n (default) m+n+16 bits (default) m+n+16 bits (default) input data register b input data register a m n n n m n n m overflow register output register accumulator multiplier multiplicand signedab shift register a in shift register b in shift register a out shift register b out output addn accumsload pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register pipeline register input register pipeline register to accumulator to accumulator to multiplier overflow signal multiplier multiplier add/sub pipe reg pipe reg n m m n m n m n n m m+n (default) m+n+1 (default) m+n+1 (default) m+n (default) x x n m m n m n n m multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 signed shift register a in shift register b in shift register a out shift register b out output addn pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register pipeline register pipeline register input data register a input data register a input data register b input data register b o u tput register to multiplier to accumulator
2-16 architecture lattice semiconductor latticeecp/ec family data sheet multaddsum sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and b1. additionally the operands a2 and b2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands a3 and b3. the result of both addition/subtraction are added in a summation block. the user can enable the input, output and pipeline registers. figure 2-17 shows the multaddsum sysdsp element. figure 2-17. multaddsum clock, clock enable and reset resources global clock, clock enable and reset signals from routing are available to every dsp block. four clock, reset and clock enable signals are selected for the sysdsp block. from four clock sources (clk0, clk1, clk2, clk3) one clock is selected for each input register, pipeline register and output register. similarly clock enable (ce) and multiplier add/sub0 x n m m+n (default) m+n (default) m+n+1 m+n+2 m+n+2 m+n+1 m+n (default) m+n (default) m n m n m n n m x n n m n n m multiplier multiplier multiplier add/sub1 x n m m n m n m n n m x n m m n m n n m sum multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 multiplier b2 multiplicand a2 multiplier b3 multiplicand a3 signed shift register b in output addn0 pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register to multiplier to add/sub0 pipeline register pipeline register input register to add/sub1 addn1 pipeline register pipeline register pipeline register shift register a in shift register b out shift register a out input data register a input data register a input data register a input data register a input data register b input data register b input data register b input data register b outp ut re gister
2-17 architecture lattice semiconductor latticeecp/ec family data sheet reset (rst) are selected from their four respective sources (ce0, ce1, ce2, ce3 and rst0, rst1, rst2, rst3) at each input register, pipeline register and output register. signed and unsigned with different widths the dsp block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. for unsigned operands, unused upper data bits should be lled to create a valid x9, x18 or x36 operand. for signed two?s complement operands, sign extension of the most signi cant bit should be performed until x9, x18 or x36 width is reached. table 2-8 provides an example of this. ta b le 2-8. an example of sign extension o verflow flag from mac the sysdsp block provides an over ow output to indicate that the accumulator has over ow ed. when two unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and over ow signal is indicated. when two positive numbers are added with a negative sum and when two negative n umbers are added with a positive sum, then the accumulator ?roll-over? is said to have occurred and an over ow signal is indicated. note when over ow occurs the over ow ag is present for only one cycle. by counting these over ow pulses in fpga logic, larger accumulators can be constructed. the conditions over ow signal for signed and unsigned operands are listed in figure 2-18. figure 2-18. accumulator over?w/under?w conditions number unsigned unsigned 9-bit unsigned 18-bit signed tw o?s complement signed 9-bits tw o?s complement signed 18-bits +5 0101 00000101 00000000 00000101 0101 00000101 00000000 00000101 -6 0110 00000110 00000000 00000110 1010 11111010 11111111 11111010 00000000 00000001 00000010 00000011 11111101 11111110 11111111 overflow signal is generated for one cycle when this boundary is crossed 0 +1 +2 +3 -3 -2 -1 unsigned operation signed operation 01111111 01111110 01111101 01111100 10000010 10000001 10000000 127 126 125 124 -126 -127 -128 00000000 00000001 00000010 00000011 11111101 11111110 11111111 carry signal is generated for one cycle when this boundary is crossed 0 1 2 3 253 254 255 01111111 01111110 01111101 01111100 10000010 10000001 10000000 127 126 125 124 130 129 128
2-18 architecture lattice semiconductor latticeecp/ec family data sheet isplever module manager the user can access the sysdsp block via the isplever module manager, which has options to con gure each dsp module (or group of modules) or through direct hdl instantiation. additionally lattice has partnered math- wo r ks to support instantiation in the simulink tool, which is a graphical simulation environment. simulink works with isplever and dramatically shortens the dsp design cycle in lattice fpgas. optimized dsp functions lattice provides a library of optimized dsp ip functions. some of the ips planned for latticeecp dsp are: bit cor- relators, fast fourier transform, finite impulse response (fir) filter, reed-solomon encoder/ decoder, turbo encoder/decoders and convolutional encoder/decoder. please contact lattice to obtain the latest list of available dsp ips. resources available in the latticeecp family ta b le 2-9 shows the maximum number of multipliers for each member of the latticeecp family. table 2-10 shows the maximum available ebr ram blocks in each of the latticeecp family. ebr blocks, together with distributed ram can be used to store variables locally for the fast dsp operations. ta b le 2-9. number of dsp blocks in latticeecp family ta b le 2-10. embedded sram in latticeecp family dsp performance of the latticeecp family ta b le 2-11 lists the maximum performance in millions of mac operations per second (mmac) for each member of the latticeecp family. ta b le 2-11. dsp block performance of latticeecp family f or further information on the sysdsp block, please see details of additional technical information at the end of this data sheet. device dsp block 9x9 multiplier 18x18 multiplier 36x36 multiplier lfecp6 4 32 16 4 lfecp10 5 40 20 5 lfecp15 6 48 24 6 lfecp20 7 56 28 7 lfecp40 10 80 40 10 device ebr sram block t otal ebr sram (kbits) lfecp6 10 92 lfecp10 30 276 lfecp15 38 350 lfecp20 46 424 lfecp40 70 645 device dsp block dsp performance mmac lfecp6 4 lfecp10 5 lfecp15 6 lfecp20 7 lfecp40 10
2-19 architecture lattice semiconductor latticeecp/ec family data sheet programmable i/o cells (pic) each pic contains two pios connected to their respective sysio buffers which are then connected to the pads as shown in figure 2-19. the pio block supplies the output data (do) and the tri-state control signal (to) to sysio b uffer, and receives input from the buffer. figure 2-19. pic diagram tw o adjacent pios can be joined to provide a differential i/o pair (labeled as ?t? and ?c?) as shown in figure 2-20. the pad labels ?t? and ?c? distinguish the two pios. only the pio pairs on the left and right edges of the device can be con gured as lvds transmit/receive pairs. one of every 16 pios contains a delay element to facilitate the generation of dqs signals. the dqs signal feeds the dqs bus which spans the set of 16 pios. the dqs signal from the bus is used to strobe the ddr data from the memory into input register blocks. this interface is designed for memories that support one dqs strobe per eight bits of data. pio b pada "t" p adb "c" opos0 oneg0 opos1 oneg1 td inck indd inff ipos0 ipos1 clk ce lsr gsrn pio a sysio buffer dqs ddrclkpol iold0 iolt0 d0 ddrclk di ipos1 ipos0 inck indd inff d0 d1 td d1 output register block (2 flip flops) t ristate register block (2 flip flops) ddrclk input register block (5 flip flops) clko clki ceo cei control muxes lsr gsr
2-20 architecture lattice semiconductor latticeecp/ec family data sheet ta b le 2-12. pio signal list figure 2-20. dqs routing pio the pio contains four blocks: an input register block, output register block, tristate register block and a control logic b lock. these blocks contain registers for both single data rate (sdr) and double data rate (ddr) operation along with the necessary clock and selection logic. programmable delay lines used to shift incoming clock and data sig- nals are also included in these blocks. name type description ce0, ce1 control from the core clock enables for input and output block ffs. clk0, clk1 control from the core system clocks for input and output blocks. lsr control from the core local set/reset. gsrn control from routing global set/reset (active low). inck input to the core input to primary clock network or pll reference inputs. dqs input to pio dqs signal from logic (routing) to pio. indd input to the core unregistered data input to core. inff input to the core registered input on positive edge of the clock (clk0). ipos0, ipos1 input to the core ddrx registered inputs to the core. oneg0 control from the core output signals from the core for sdr and ddr operation. opos0, control from the core output signals from the core for ddr operation opos1 oneg1 tristate control from the core signals to tristate register block for ddr operation. td tristate control from the core tristate signal from the core used in sdr operation. ddrclkpol control from clock polarity bus controls the polarity of the clock (clk0) that feed the ddr input block. pio a pio b pa da "t" p adb "c" pio b pio a pio b pio a assigned dqs pin dqs sysio buffer lv d s p air pa da "t" p adb "c" lv d s p air pa da "t" p adb "c" lv d s pair pio a pio b pa da "t" p adb "c" lv d s p air pio a pio b pa da "t" p adb "c" lv ds pair pio a pio b pa da "t" p adb "c" lv d s p air pio a pio b pa da "t" p adb "c" lv d s p air pio a pio b pa da "t" p adb "c" l vds pair delay
2-21 architecture lattice semiconductor latticeecp/ec family data sheet input register block the input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. figure 2-21 shows the diagram of the input register block. input signals are fed from the sysio buffer to the input register block (as signal di). if desired the input signal can b ypass the register and delay elements and be used directly as a combinatorial signal (indd), a clock (inck) and in selected blocks the input to the dqs delay block. if one of the bypass options is not chosen, the signal rst passes through an optional delay block. this delay, if selected, reduces input-register hold-time requirement when using a global clock. the input block allows two modes of operation. in the single data rate (sdr) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. in the ddr mode two registers are used to sample the data on the positive and negative edges of the dqs signal creating two data streams, d0 and d2. these two data streams are synchronized with the system clock before entering the core. further discussion on this topic is in the ddr memory section of this data sheet. figure 2-22 shows the input register waveforms for ddr operation and figure 2-23 shows the design tool primi- tives. the sdr/sync registers have reset and clock enable available. the signal ddrclkpol controls the polarity of the clock used in the synchronization registers. it ensures ade- quate timing when data is transferred from the dqs to system clock domain. for further discussion on this topic, see the ddr memory section of this data sheet. figure 2-21. input register diagram d q d q d q d-type fixed delay to routing di (from sysio buffer) dqs delayed (from dqs bus) clk0 (from routing) ddrclkpol (from ddr p olarity control bus) inck indd delay block ddr registers d-type d-type d q d q d-type /latch /latch d-type ipos0 ipos1 sdr & sync registers d0 d2 d1
2-22 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-22. input register ddr waveforms figure 2-23. inddrxb primative abcde f bd di (in ddr mode) d0 d2 dqs a c dqs delayed iddrxb lsr qa d eclk qb ddrclkpol sclk ce
2-23 architecture lattice semiconductor latticeecp/ec family data sheet output register block the output register block provides the ability to register signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation that is combined with an additional latch for ddr operation. figure 2-24 shows the diagram of the output register block. in sdr mode, oneg0 feeds one of the ip- ops that then feeds the output. the ip- op can be con gured a d- type or latch. in ddr mode, oneg0 is fed into one register on the positive edge of the clock and opos0 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). figure 2-25 shows the design tool ddr primitives. the sdr output register has reset and clock enable available. the additional register for ddr operation does not have reset or clock enable available. figure 2-24. output register block figure 2-25. oddrxb primative d q d q d-type oneg0 from routing clk1 programmed control do latch le* *latch is transparent when input is low. opos0 outddn /latch 0 1 0 1 to sysio buffer oddrxb lsr q db clk da
2-24 architecture lattice semiconductor latticeecp/ec family data sheet t ristate register block the tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation and an additional latch for ddr operation. figure 2-26 shows the diagram of the tristate register block. in sdr mode, oneg1 feeds one of the ip- ops that then feeds the output. the ip- op can be con gured a d- type or latch. in ddr mode, oneg1 is fed into one register on the positive edge of the clock and opos1 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). figure 2-26. tristate register block control logic block the control logic block allows the selection and modi cation of control signals for use in the pio block. a clock is selected from one of the clock signals provided from the general purpose routing and a dqs signal provided from the programmable dqs pin. the clock can optionally be inverted. the clock enable and local reset signals are selected from the routing and optionally inverted. the global tristate signal is passed through this block. ddr memory support implementing high performance ddr memory interfaces requires dedicated ddr register structures in the input (for read operations) and in the output (for write operations). as indicated in the pio logic section, the ec devices provide this capability. in addition to these registers, the ec devices contain two elements to simplify the design of input structures for read operations: the dqs delay block and polarity control logic. dll calibrated dqs delay block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces a pll is used for this adjustment, however in ddr memories the clock (referred to as dqs) is not free running so this approach cannot be used. the dqs delay block provides the required clock alignment for ddr memory interfaces. d le* q d q d-type oneg1 clk1 programmed control to latch *latch is transparent when input is low. opos1 outddn /latch 0 1 0 1 from routing to sysio buffer td
2-25 architecture lattice semiconductor latticeecp/ec family data sheet the dqs signal (selected pios only) feeds from the pad through a dqs delay element to a dedicated dqs rout- ing resource. the dqs signal also feeds polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. figures 2-27 and 2-28 show how the dqs transition signals are routed to the pios. the temperature, voltage and process variations of the dqs delay block are compensated by a set of calibration (6-bit bus) signals from two dlls on opposite sides of the device. each dll compensates dqs delays in its half of the device as shown in figure 2-28. the dll loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. figure 2-27. dqs local bus. di clki cei pio gsr dqs input register block ( 5 flip flops) to sync. reg. dqs to ddr reg. dqs strobe pa d ddr datain pa d sysio buffer di sysio buffer pio dqsdel p olarity control logic dqs calibration bus from dll delay control bus p olarity control bus dqs bus
2-26 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-28. dll calibration bus and dqs/dqs transition distribution p olarity control logic in a typical ddr memory interface design, the phase relation between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unknown. the latticeecp/ec family contains dedicated circuits to transfer data between these domains. to prevent setup and hold violations at the domain transfer between dqs (delayed) and the system clock a clock polarity selector is used. this changes the edge on which the data is registered in the synchronizing registers in the input register b lock. this requires evaluation at the start of each read cycle for the correct clock polarity. prior to the read operation in ddr memories dqs is in tristate (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit detects this transition. this signal is used to control the polarity of the clock to the synchronizing registers. sysio buffer each i/o is associated with a e xible buffer referred to as a sysio buffer. these buffers are arranged around the periphery of the device in eight groups referred to as banks. the sysio buffers allow users to implement the wide va r iety of standards that are found in today?s systems including lvcmos, sstl, hstl, lvds and lvpecl. sysio buffer banks latticeecp/ec devices have eight sysio buffer banks; each is capable of supporting multiple i/o standards. each sysio bank has its own i/o supply voltage (v ccio ), and two voltage references v ref1 and v ref2 resources allow- ing each bank to be completely independent from each other. figure 2-29 shows the eight banks and their associ- ated supplies. in the latticeecp/ec devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos, pci and pci- x) are powered using v ccio. l vttl, lvcmos33, lvcmos25 and lvcmos12 can also be set as x ed threshold dll dll po larity control bus dqs bus delay control bus
2-27 architecture lattice semiconductor latticeecp/ec family data sheet input independent of v ccio. in addition to the bank v ccio supplies, the latticeecp/ec devices have a v cc core logic power supply, and a v ccaux supply that power all differential and referenced buffers. each bank can support up to two separate vref voltages, vref1 and vref2 that set the threshold for the refer- enced input buffers. in the latticeecp/ec devices, some dedicated i/o pins in a bank can be con gured to be a reference voltage supply pin. each i/o is individually con gurable based on the bank?s supply and reference volt- ages. figure 2-29. latticeecp/ec banks v ref1(2) gnd bank 2 v ccio2 v ref2(2) v ref1(3) gnd bank 3 v ccio3 v ref2(3) v ref1(7) gnd bank 7 v ccio7 v ref2(7) v ref1(6) gnd note: n and m are the maximum number of i/os per bank. bank 6 v ccio6 v ref2(6) v ref1( 5) gnd bank 5 v ccio5 v ref2( 5) v ref1( 4) gnd bank 4 v ccio4 v ref2( 4) v ref1( 0) gnd bank 0 v ccio 0 v ref2( 0) v ref1(1) gnd bank 1 v ccio 1 v ref2 (1) m
2-28 architecture lattice semiconductor latticeecp/ec family data sheet latticeecp/ec devices contain two types of sysio buffer pairs. 1. t op and bottom sysio buffer pair (single-ended outputs only) the sysio buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). the referenced input buffer can also be con gured as a differential input. the two pads in the pair are described as ?true? and ?comp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. only the i/os on the top and bottom banks have pci clamp. 2. left and right sysio buffer pair (differential and single-ended outputs) the sysio buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. the refer- enced input buffer can also be con gured as a differential input. in these banks the two pads in the pair are described as ?true? and ?comp?, where the true pad is associated with the positive side of the differential i/o, and the comp (complementary) pad is associated with the negative side of the differential i/o. only the left and right banks have lvds differential output drivers. supported standards the latticeecp/ec sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl and other standards. the buffers support the lvttl, lvcmos 1.2, 1.5, 1.8, 2.5 and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individually con gurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. other single-ended standards supported include sstl and hstl. differential standards supported include lvds, blvds, lvpecl, differential sstl and differential hstl. tables 2-13 and 2-14 show the i/o standards (together with their supply and reference voltages) supported by the latticeecp/ec devices. for further information on utiliz- ing the sysio buffer to support a variety of standards please see the details of additional technical information at the end of this data sheet.
2-29 architecture lattice semiconductor latticeecp/ec family data sheet ta b le 2-13. supported input standards input standard v ref (nom.) v ccio 1 (nom.) single ended interfaces l vttl ? ? l vcmos33 2 ?? l vcmos25 2 ?? l vcmos18 ? 1.8 l vcmos15 ? 1.5 l vcmos12 2 ?? pci ? 3.3 hstl18 class i, ii 0.9 ? hstl18 class iii 1.08 ? hstl15 class i 0.75 ? hstl15 class iii 0.9 ? sstl3 class i, ii 1.5 ? sstl2 class i, ii 1.25 ? sstl18 class i 0.9 ? differential interfaces differential sstl18 class i ? ? differential sstl2 class i, ii ? ? differential sstl3 class i, ii ? ? differential hstl15 class i, iii ? ? differential hstl18 class i, ii, iii ? ? l vds, lvpecl ? ? blvds ? ? 1. when not speci ed v ccio can be set anywhere in the valid operating range. 2. jtag inputs do not have a x ed threshold option and always follow v ccj.
2-30 architecture lattice semiconductor latticeecp/ec family data sheet ta b le 2-14. supported output standards hot socketing the latticeecp/ec devices have been carefully designed to ensure predictable behavior during power-up and power-down. power supplies can be sequenced in any order. during power up and power-down sequences, the i/os remain in tristate until the power supply voltage is high enough to ensure reliable operation. in addition, leakage into i/o pins is controlled to within speci ed limits, this allows for easy integration with the rest of the system. these capabilities make the latticeecp/ec ideal for many multiple power supply and hot-swap applica- tions. output standard drive v ccio (nom.) single-ended interfaces l vttl 4ma, 8ma, 12ma, 16ma, 20ma 3.3 l vcmos33 4ma, 8ma, 12ma 16ma, 20ma 3.3 l vcmos25 4ma, 8ma, 12ma, 16ma, 20ma 2.5 l vcmos18 4ma, 8ma, 12ma, 16ma 1.8 l vcmos15 4ma, 8ma 1.5 l vcmos12 2ma, 6ma 1.2 l vcmos33, open drain 4ma, 8ma, 12ma 16ma, 20ma ? l vcmos25, open drain 4ma, 8ma, 12ma 16ma, 20ma ? l vcmos18, open drain 4ma, 8ma, 12ma 16ma ? l vcmos15, open drain 4ma, 8ma ? l vcmos12, open drain 2ma, 6ma ? pci33 n/a 3.3 hstl18 class i, ii, iii n/a 1.8 hstl15 class i, iii n/a 1.5 sstl3 class i, ii n/a 3.3 sstl2 class i, ii n/a 2.5 sstl18 class i n/a 1.8 differential interfaces differential sstl3, class i, ii n/a 3.3 differential sstl2, class i, ii n/a 2.5 differential sstl18, class i n/a 1.8 differential hstl18, class i, ii, iii n/a 1.8 differential hstl15, class i, iii n/a 1.5 l vds n/a 2.5 blvds 1 n/a 2.5 l vpecl 1 n/a 3.3 1. emulated with external resistors.
2-31 architecture lattice semiconductor latticeecp/ec family data sheet con guration and testing the following section describes the con guration and testing features of the latticeecp/ec family of devices. ieee 1149.1-compliant boundary scan testability all latticeecp/ec devices have boundary scan cells that are accessed through an ieee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri cation. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port has its own supply voltage v ccj and can operate with lvcmos3.3, 2.5, 1.8, 1.5 and 1.2 standards. f or more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. device con guration all latticeecp/ec devices contain two possible ports that can be used for device con guration. the test access port (tap), which supports bit-wide con guration, and the sysconfig port that supports both byte-wide and serial con guration. the tap supports both the ieee std. 1149.1 boundary scan speci cation and the ieee std. 1532 in-system con- guration speci cation. the sysconfig port is a 20-pin interface with six of the i/os used as dedicated pins and the rest being dual-use pins. when sysconfig mode is not used, these dual-use pins are available for general purpose i/o. there are four con guration options for latticeecp/ec devices: 1. industry standard spi memories. 2. industry standard byte wide ash and ispmach 4000 for control/addressing. 3. con guration from system microprocessor via the con guration bus or tap. 4. industry standard fpga board memory. on power-up, the fpga sram is ready to be con gured with the sysconfig port active. the ieee 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the tap port. once a con guration port is selected, that port is locked and another con guration port cannot be activated until the next power-up sequence. f or more information on device con guration, please see details of additional technical documentation at the end of this data sheet. internal logic analyzer capability (isptracy) all latticeecp/ec devices support an internal logic analyzer diagnostic feature. the diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. this feature is enabled by lattice?s isptracy. the isptracy utility is added into the user design at com- pile time. f or more information on isptracy, please see information regarding additional technical documentation at the end of this data sheet. external resistor latticeecp/ec devices require a single external, 10k ohm +/- 1% value between the xres pin and ground. device con guration will not be completed if this resistor is missing. there is no boundary scan register on the e xternal resistor pad.
2-32 architecture lattice semiconductor latticeecp/ec family data sheet oscillator every latticeecp/ec device has an internal cmos oscillator which is used to derive a master serial clock for con- guration. the oscillator and the master serial clock run continuously. the default value of the master serial clock is 2.5mhz. table 2-15 lists all the available master serial clock frequencies. when a different master serial clock is selected during the design process, the following sequence takes place: 1. user selects a different master serial clock frequency. 2. during con guration the device starts with the default (2.5mhz) master serial clock frequency. 3. the clock con guration settings are contained in the early con guration bit stream. 4. the master serial clock frequency changes to the selected frequency once the clock con guration bits are received. f or further information on the use of this oscillator for con guration, please see details of additional technical docu- mentation at the end of this data sheet. ta b le 2-15. selectable master serial clock (cclk) frequencies during con?uration density shifting the latticeecp/ec family has been designed to ensure that different density devices in the same package have the same pin-out. furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. in many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. however, the exact details of the nal resource utiliza- tion will impact the likely success in each case. cclk (mhz) cclk (mhz) cclk (mhz) 2.5* 13 45 4.3 15 51 5.4 20 55 6.9 26 60 8.1 30 130 9.2 34 ? 10.0 41 ?
www.latticesemi.com 3-1 dc and switching_01 j une 2004 advance data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. recommended operating conditions absolute maximum ratings 1, 2, 3 1. stress above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci cation is not implied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v supply voltage v ccaux . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccj . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . . . . . . -0.5 to 3.75v input voltage applied 4 . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.25v i/o tristate voltage applied 4 . . . . . . . . . . . . . . . . . -0.5 to 3.75v storage temperature (ambient) . . . . . . . . . . . . . . -65 to 150c j unction temp. (tj) +125c 4. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20ns. symbol parameter min. max. units v cc core supply voltage 1.14 1.26 v v ccaux a uxiliary supply voltage 3.135 3.465 v v ccio 1, 2 i/o driver supply voltage 1.140 3.465 v v ccj 1 supply voltage for ieee 1149.1 test access port 1.140 3.465 v t jcom j unction commercial operation 0 +85 c t jind j unction industrial operation -40 100 c 1. if v ccio or v ccj is set to 1.2v, they must be connected to the same power supply as v cc. if v ccio or v ccj is set to 3.3v, they must be con- nected to the same power supply as v ccaux . 2. see recommended voltages by i/o standard in subsequent table. hot socketing speci cations 1, 2, 3, 4 1. insensitive to sequence of v cc, v ccaux and v ccio . however, assumes monotonic rise/fall rates for v cc, v ccaux and v ccio. 2. 0 v cc v cc (max), 0 v ccio v ccio (max) or 0 v ccaux v ccaux (max). 3. i dk is additive to i pu, i pw or i bh . 4. lvcmos and lvttl only. symbol parameter condition min. typ. max units i dk input or i/o leakage current 0 v in v ih (max) ? ? +/-1000 a latticeecp/ec family data sheet dc and switching characteristics
3-2 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet dc electrical characteristics over recommended operating conditions symbol parameter condition min. typ. max. units i il, i ih 1 input or i/o low leakage 0 v in (v ccio - 0.2v) ? ? 10 a (v ccio - 0.2v) v in 3.6v ? ? 40 a i pu i/o active pull-up current 0 v in 0.7 v ccio 30 ? 150 a i pd i/o active pull-down current v il (max) v in v ih (max) -30 ? -150 a i bhls bus hold low sustaining current v in = v il (max) 30 ? ? a i bhhs bus hold high sustaining current v in = 0.7v ccio -30 ? ? a i bhlo bus hold low overdrive current 0 v in v ih (max) ? ? 150 a i bhlh bus hold high overdrive current 0 v in v ih (max) ? ? -150 a v bht bus hold trip points 0 v in v ih (max) v il (max) ? v ih (min) v c1 i/o capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?8?pf c2 dedicated input capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?6?pf 1. input or i/o leakage current is measured with the pin con gured as an input or as an i/o with the output driver tri-stated. it is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a 25c, f = 1.0mhz supply current (standby) 1, 2, 3 over recommended operating conditions 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all outputs are tristated, all inputs are con gured as lvcmos and held at the v ccio or gnd. 3. frequency 0mhz. symbol parameter condition typ. max. units i cc core power supply current lfec1 ma lfec3 ma lfec6/lfecp6 ma lfec10/lfecp10 ma lfec15/lfecp15 ma lfec20/lfecp20 60 ma lfec40/lfecp40 ma i ccaux a uxiliary power supply current lfec1 ma lfec3 ma lfec6/lfecp6 ma lfec10/lfecp10 ma lfec15/lfecp15 ma lfec20/lfecp20 15 ma lfec40/lfecp40 ma i ccpll pll power supply lfec1, lfec3, lfec6, lfecp6 ma lfec10, lfec15, lfec20, lfec40, lfecp10, lfecp15, lfecp20, lfecp40 ma i ccio bank power supply current 15 ma i ccj v ccj power supply current 1 ma
3-3 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet sysio recommended operating conditions initialization supply current 1 over recommended operating conditions 1. until done signal is active. symbol parameter condition typ. max. units i cc core power supply current lfec1 ma lfec3 ma lfec6/lfecp6 ma lfec10/lfecp10 ma lfec15/lfecp15 ma lfec20/lfecp20 ma lfec40/lfecp40 ma i ccaux a uxiliary power supply current lfec1 ma lfec3 ma lfec6/lfecp6 ma lfec10/lfecp10 ma lfec15/lfecp15 ma lfec20/lfecp20 ma lfec40/lfecp40 ma i ccpll pll power supply lfec1, lfec3, lfec6, lfecp6 ma lfec10, lfec15, lfec20, lfec40, lfecp10, lfecp15, lfecp20, lfecp40 ma i ccio bank power supply current ma i ccj v ccj power supply current ma v ccio v ref (v) standard min. typ. max. min. typ. max. l vcmos 3.3 3.135 3.3 3.465 ? ? ? l vcmos 2.5 2.375 2.5 2.625 ? ? ? l vcmos 1.8 1.71 1.8 1.89 ? ? ? l vcmos 1.5 1.425 1.5 1.575 ? ? ? l vcmos 1.2 1.14 1.2 1.26 ? ? ? l vttl 3.135 3.3 3.465 ? ? ? pci 3.135 3.3 3.465 ? ? ? sstl18 class i 1.71 2.5 1.89 1.15 1.25 1.35 sstl2 class i, ii 2.375 2.5 2.625 1.15 1.25 1.35 sstl3 class i, ii 3.135 3.3 3.465 1.3 1.5 1.7 hstl15 class i 1.425 1.5 1.575 0.68 0.75 0.9 hstl15 class iii 1.425 1.5 1.575 ? 0.9 ? hstl 18 class i, ii 1.71 1.8 1.89 ? 0.9 ? hstl 18 class iii 1.71 1.8 1.89 ? 1.08 ? l vds 2.375 2.5 3.625 ? ? ? l vpecl 1 3.135 3.3 3.465 ? ? ? blvds 1 2.375 2.5 2.625 ? ? ? 1. inputs on chip. outputs are implemented with the addition of external resisters.
3-4 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet sysio single-ended dc electrical characteristics input/output standard v il v ih v ol max. (v) v oh min. (v) i ol 1 (ma) i oh 1 (ma) min. (v) max. (v) min. (v) max. (v) l vcmos 3.3 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vttl -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vcmos 1.8 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vcmos 1.5 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vcmos 1.2 -0.3 0.35v cc 0.65v cc 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 pci -0.3 0.3v ccio 0.5v ccio 3.6 0.1v ccio 0.9v ccio 1.5 -0.5 sstl3 class i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v ccio - 1.1 8 -8 sstl3 class ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v ccio - 0.9 16 -16 sstl2 class i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 7.6 -7.6 sstl2 class ii -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v ccio - 0.43 15.2 -15.2 sstl18 class i -0.3 v ref - 0.125 v ref + 0.125 3.6 0.4 v ccio - 0.4 6.7 -6.7 hstl15 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 8 -8 hstl15 class iii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 24 -8 hstl18 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 9.6 -9.6 hstl18 class ii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 16 -16 hstl18 class iii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 24 -8 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma. where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank.
3-5 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet sysio differential electrical characteristics l vds over recommended operating conditions p arameter symbol parameter description test conditions min. typ. max. units v inp, v inm input voltage 0 ? 2.4 v v thd differential input threshold +/-100 ? ? mv v cm input common mode voltage 100mv v thd v thd /2 1.2 1.8 v 200mv v thd v thd /2 1.2 1.9 v 350mv v thd v thd /2 1.2 2.0 v i in input current power on or power off ? ? +/-10 a v oh output high voltage for v op or v om r t = 100 ohm ? 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohm 0.9v 1.03 ? v v od output voltage differential (v op - v om ), r t = 100 ohm 250 350 450 mv ? v od change in v od between high and low ??50 mv v os output voltage offset (v op - v om )/2, r t = 100 ohm 1.125 1.25 1.375 v ? v os change in v os between h and l ? ? 50 mv i osd output short circuit current v od = 0v driver outputs shorted ?? 6ma
3-6 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet differential hstl and sstl differential hstl and sstl outputs are implemented as a pair of complementary single-ended outputs. all allow- able single-ended output classes (class i and class ii) are supported in this mode. blvds the latticeecp/ec devices support blvds standard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel external resistor across the driver outputs. blvds is intended for use when m ulti-drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-1 is one possible solution for bi-directional multi-point differential signals. figure 3-1. blvds multi-point output example ta b le 3-1. blvds dc conditions 1 over recommended operating conditions t ypical p arameter description zo = 45 zo = 90 units z out output impedance 100 100 ohm r tleft left end termination 45 90 ohm r tright right end termination 45 90 ohm v oh output high voltage 1.375 1.48 v v ol output low voltage 1.125 1.02 v v od output differential voltage 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.2 10.2 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v 80 80 80 80 80 80 45-90 ohms 45-90 ohms 80 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + -
3-7 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet l vpecl the latticeecp/ec devices support differential lvpecl standard. this standard is emulated using complemen- tary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-2 is one possible solution for point-to-point signals. figure 3-2. differential lvpecl ta b le 3-2. lvpecl dc conditions 1 over recommended operating conditions f or further information on lvpecl, blvds and other differential interfaces please see details of additional techni- cal information at the end of this data sheet. p arameter description typical units z out output impedance 100 ohm r p driver parallel resistor 150 ohm r t receiver termination 100 ohm v oh output high voltage 2.03 v v ol output low voltage 1.27 v v od output differential voltage 0.76 v v cm output common mode voltage 1.65 v z back back impedance 85.7 ohm i dc dc output current 12.7 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential 100 ohms 100 ohms 100 ohms off-chip 3.3v 3.3v + - ~150 ohms
3-8 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet rsds the latticeecp/ec devices support differential rsds standard. this standard is emulated using complementary l vcmos outputs in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-3 is one possible solution for rsds standard implementation. use lvds25e mode with suggested resistors for rsds operation. resistor values in figure 3-3 are industry standard values for 1% resistors. figure 3-3. rsds (reduced swing differential standard) ta b le 3-3. rsds dc conditions 5v tolerant input buffer the input buffers of the latticeecp/ec family of devices can support 5v signals by using a pci clamp and an e xternal series resistor as shown in figure 3-4. a suitable resistor can be selected by using the pci clamp charac- teristic as shown in figure 3-5. figure 3-4. 5 v tolerant input buffer p arameter description typical units z out output impedance ohm r s driver series resistor ohm r p driver parallel resistor ohm r t receiver termination ohm v oh output high voltage v v ol output low voltage v v od output differential voltage v v cm output common mode voltage v z back back impedance ohm i dc dc output current ma 100 294 294 on-chip emulated rsds buffer vccio = 2.5v vccio = 2.5v zo = 100 + - 121 off-chip external resistor 5v signals from legacy systems 3.3v
3-9 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet figure 3-5. typical pci clamp current voltage (v) 100 200 300 400 50 0 1 0 2345678 150 250 350 current (ma)
3-10 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet t ypical building block function performance pin-to-pin performance (lvcmos25 12ma drive) function -5 timing units basic functions 16-bit decoder 6.8 ns 32-bit decoder 7.8 ns 64-bit decoder 8.4 ns 4:1 mux 5.7 ns 8:1 mux 5.9 ns 16:1 mux 6.5 ns 32:1 mux 6.9 ns combinatorial (pin to lut to pin) 5.3 ns embedded memory functions pin to ebr input register setup 0.0 ns ebr output clock to pin 11.3 ns distributed pfu ram pin to pfu ram register setup 0.0 ns pfu ram clock to pin 6.8 ns register-to-register performance function -5 timing units basic functions 16-bit decoder 263 mhz 32-bit decoder 230 mhz 64-bit decoder 211 mhz 4:1 mux 500 mhz 8:1 mux 375 mhz 16:1 mux 360 mhz 32:1 mux 373 mhz 8-bit adder 314 mhz 16-bit adder 251 mhz 64-bit adder 146 mhz 16-bit counter 360 mhz 32-bit counter 280 mhz 64-bit counter 180 mhz 64-bit accumulator 125 mhz embedded memory functions 256x36 single port ram 305 mhz 512x18 true-dual port ram 308 mhz distributed memory functions 16x2 single port ram 455 mhz 64x2 single port ram 244 mhz 128x4 single port ram 196 mhz 32x2 pseudo-dual port ram 341 mhz 64x4 pseudo-dual port ram 303 mhz
3-11 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet derating timing tables logic timing provided in the following sections of the data sheet and the isplever design tools are worst-case n umbers in the operating range. actual delays at nominal temperature and voltage for best-case process, can be m uch better than the values given in the tables. to calculate logic timing numbers at a particular temperature and v oltage multiply the noted numbers with the derating factors provided below. the junction temperature for the fpga depends on the power dissipation by the device, the package thermal char- acteristics ( ja ), and the ambient temperature, as calculated with the following equation: t jmax = t amax + (power * ja ) the user must determine this temperature and then use it to determine the derating factor based on the following derating tables: t j c. ta b le 3-4. delay derating table for internal blocks dsp function 9x9 pipelined multiply/accumulate 1 265 mhz 18x18 pipelined multiply/accumulate 1 226 mhz 36x36 pipelined multiply 1 177 mhz 1. applies to latticeecp devices only. t j c commercial t j c industrial po wer supply voltage 1.14v 1.2v 1.26v ? -40 ? -25 015 25 40 85 100 100 115 110 125 125 ? register-to-register performance (continued) function -5 timing units
3-12 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec external switching characteristics over recommended operating conditions p arameter description device -5 -4 -3 units min. max. min. max. min. max. general i/o pin parameters (using primary clock without pll) 1 t co clock to output - pio output register lfec20 ? 6.75 - 8.43 ? 11.25 ns t su clock to data setup - pio input register lfec20 0.00 ? 0.00 ? 0.00 ? ns t h clock to data hold - pio input register lfec20 2.55 ? 3.19 ? 4.25 ? ns t su_del clock to data setup - pio input register with data input delay lfec20 2.85 ? 3.42 ? 3.99 ? ns t h_del clock to data hold - pio input register with input data delay lfec20 0.00 ? 0.00 ? 0.00 ? ns f max_io clock frequency of i/o and pfu register lfec20 ? ? ? mhz ddr i/o pin parameters 2 t d vbdq data valid before dqs (ddr read) lfec20 ? ? ? ps t dv adq data valid after dqs (ddr read) lfec20 ? ? ? ps t dq_sk data skew (ddr write) lfec20 ? ? ? ps t dqs_jit dqs jitter (ddr write) lfec20 ? ? ? ps f max_ddr ddr clock frequency lfec20 ? 166 ? ? mhz 1. general timing numbers based on lvcmos2.5v, 12 ma. 2. ddr timing numbers based on sstl i/o.
3-13 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec internal timing parameters 1 over recommended operating conditions p arameter description -5 -4 -3 units min. max. min. max. min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f output) ? 0.25 ? 0.31 ? 0.36 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) ? 0.55 ? 0.66 ? 0.77 ns t lsr_pfu set/reset to output of pfu ? 0.81 ? 0.98 ? 1.14 ns t sum_pfu clock to mux (m0,m1) input setup time 0.08 ? 0.10 ? 0.11 ? ns t hm_pfu clock to mux (m0,m1) input hold time -0.06 ? -0.07 ? -0.08 ? ns t sud_pfu clock to d input setup time 0.09 ? 0.10 ? 0.12 ? ns t hd_pfu clock to d input hold time -0.04 ? -0.04 - -0.05 ? ns t ck2q_pfu clock to q delay, d-type register con gura- tion ? 0.43 ? 0.51 ? 0.60 ns t le2q_pfu clock to q delay latch con guration ? 0.54 ? 0.65 ? 0.76 ns t ld2q_pfu d to q throughput delay when latch is enabled ? 0.50 ? 0.60 ? 0.69 ns pfu memory mode timing t coram_pfu clock to output ? 0.43 ? 0.51 ? 0.60 ns t sudata_pfu data setup time -0.25 ? -0.30 ? -0.34 ? ns t hdata_pfu data hold time -0.06 ? -0.07 ? -0.08 ? ns t suaddr_pfu address setup time -0.66 ? -0.79 ? -0.92 ? ns t haddr_pfu address hold time -0.27 ? -0.33 ? -0.38 ? ns t suwren_pfu write/read enable setup time -0.30 ? -0.36 ? -0.42 ? ns t hwren_pfu write/read enable hold time -0.21 ? -0.25 ? -0.29 ? ns pic timing pio input/output buffer timing t in_pio input buffer delay ? ? ? ns t out_pio output buffer delay ? ? ? ns iologic input/output timing t sui_pio input register setup time (data before clock) ? 0.12 ? 0.14 ? 0.17 ns t hi_pio input register hold time (data after clock) ? -0.09 ? -0.11 ? -0.13 ns t coo_pio output register clock to output delay ? 0.75 ? 0.90 ? 1.05 ns t suce_pio input register clock enable setup time ? -0.02 ? -0.02 ? -0.03 ns t hce_pio input register clock enable hold time ? 0.12 ? 0.14 ? 0.17 ns t sulsr_pio set/reset setup time 0.10 0.24 0.12 0.29 0.14 0.34 ns t hlsr_pio set/reset hold time -0.24 -0.10 -0.29 -0.12 -0.34 -0.14 ns ebr timing t co_ebr clock to output from address or data ? 3.80 ? 4.55 ? 5.31 ns t coo_ebr clock to output from ebr output register ? ? ? ns ts udata_ebr setup data to ebr memory -0.34 ? -0.41 ? -0.48 ? ns t hdata_ebr hold data to ebr memory 0.37 ? 0.44 ? 0.52 ? ns t suaddr_ebr setup address to ebr memory -0.34 ? -0.41 ? -0.48 ? ns t haddr_ebr hold address to ebr memory 0.37 ? 0.45 ? 0.52 ? ns t suwren_ebr setup write/read enable to pfu memory -0.22 ? -0.26 ? -0.30 ? ns
3-14 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet t hwren_ebr hold write/read enable to pfu memory 0.23 ? 0.28 ? 0.33 ? ns t suce_ebr clock enable setup time to ebr output register 0.18 ? 0.21 ? 0.25 ? ns t hce_ebr clock enable hold time to ebr output register -0.17 ? -0.20 ? -0.24 ? ns t rsto_ebr reset to output delay time from ebr out- put register ? 1.47 ? 1.76 ? 2.05 ns pll parameters t rstrec reset recovery to rising clock ? ? ? ns t rstsu reset signal setup time 1?1?1?ns t rstw reset signal pulse width 1.8 ? 1.8 ? 1.8 ? ns dsp block timing 2 t sui_dsp input register setup time ? ? ? ns t hi_dsp input register hold time ? ? ? ns t sup_dsp pipeline register setup time ? ? ? ns t hp_dsp pipeline register hold time ? ? ? ns t suo_dsp output register setup time ? ? ? ns t ho_dsp output register hold time ? ? ? ns t coi_dsp input register clock to output time ? ? ? ns t cop_dsp pipeline register clock to output time ? ? ? ns t coo_dsp output register clock to output time ? ? ? ns t coovrfl_dsp over ow register clock to output time ? ? ? ns t suadsub adsub setup time ? ? ? ns t hadsub adsub hold time ? ? ? ns t susign sign setup time ? ? ? ns t hsign sign hold time ? ? ? ns t suaccsload accumulator load setup time ? ? ? ns t haccsload accumulator load hold time ? ? ? ns 1. internal parameters are characterized but not tested on every device. 2. these parameters apply to latticeecp devices only. latticeecp/ec internal timing parameters 1 (continued) over recommended operating conditions p arameter description -5 -4 -3 units min. max. min. max. min. max.
3-15 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet timing diagrams pfu timing diagrams figure 3-6. slice single/dual port write cycle timing figure 3-7. slice single /dual port read cycle timing ck d wre d di[1:0] do[1:0] ad ad[3:0] old data wre d do[1:0] ad ad[3:0] old data
3-16 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet ebr memory timing diagrams figure 3-8. read/write mode (normal) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-9. read/write mode with input and output registers a0 a1 a0 a1 d0 d1 doa a0 t access t access t su t h d0 d1 d0 dia ada wea csa clka a0 a1 a0 a0 d0 d1 d0 d0 doa output is only updated during a read cycle a1 d1 d0 d1 mem(n) data from previous read mem(n) data from previous read dia ada wea csa clka doa doa (regs) t su t h t access t access
3-17 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet figure 3-10. read before write (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-11. write through (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. a0 a1 a0 a1 d0 d1 d2 doa a0 d2 d3 d1 old a0 data old a1 data d0 d1 dia ada wea csa clka t su t h t access t access t access t access t access a0 a1 a0 d0 d1 d4 t su t access t access t access t h d2 d3 d4 d0 d1 d2 data from prev read or write three consecutive writes to a0 d3 doa dia ada wea csa clka t access
3-18 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec family timing adders 1 over recommended operating conditions buffer type description -5 -4 -3 units input adjusters l vds25 lvds 0.41 0.50 0.58 ns blvds25 blvds 0.41 0.50 0.58 ns l vpecl33 lvpecl 0.50 0.60 0.70 ns hstl18_i hstl_18 class i 0.41 0.49 0.57 ns hstl18_ii hstl_18 class ii 0.41 0.49 0.57 ns hstl18_iii hstl_18 class iii 0.41 0.49 0.57 ns hstl18d_i differential hstl 18 class i 0.37 0.44 0.52 ns hstl18d_ii differential hstl 18 class ii 0.37 0.44 0.52 ns hstl18d_iii differential hstl 18 class iii 0.37 0.44 0.52 ns hstl15_i hstl_15 class i 0.40 0.48 0.56 ns hstl15_iii hstl_15 class iii 0.40 0.48 0.56 ns hstl15d_i differential hstl 15 class i 0.37 0.44 0.51 ns hstl15d_iii differential hstl 15 class iii 0.37 0.44 0.51 ns sstl33_i sstl_3 class i 0.46 0.55 0.64 ns sstl33_ii sstl_3 class ii 0.46 0.55 0.64 ns sstl33d_i differential sstl_3 class i 0.39 0.47 0.55 ns sstl33d_ii differential sstl_3 class ii 0.39 0.47 0.55 ns sstl25_i sstl_2 class i 0.43 0.51 0.60 ns sstl25_ii sstl_2 class ii 0.43 0.51 0.60 ns sstl25d_i differential sstl_2 class i 0.38 0.45 0.53 ns sstl25d_ii differential sstl_2 class ii 0.38 0.45 0.53 ns sstl18_i sstl_18 class i 0.40 0.48 0.56 ns sstl18d_i differential sstl_18 class i 0.37 0.44 0.51 ns l vttl33 lvttl 0.07 0.09 0.10 ns l vcmos33 lvcmos 3.3 0.07 0.09 0.10 ns l vcmos25 lvcmos 2.5 0.00 0.00 0.00 ns l vcmos18 lvcmos 1.8 0.07 0.09 0.10 ns l vcmos15 lvcmos 1.5 0.24 0.29 0.33 ns l vcmos12 lvcmos 1.2 1.27 1.52 1.77 ns pci33 pci 0.07 0.09 0.10 ns output adjusters l vds25e lvds 2.5 e ns l vds25 lvds 2.5 ns blvds25 blvds 2.5 ns l vpecl33 lvpecl 3.3 ns hstl18_i hstl_18 class i ns hstl18_ii hstl_18 class ii ns hstl18_iii hstl_18 class iii ns hstl18d_i differential hstl 18 class i ns hstl18d_ii differential hstl 18 class ii ns hstl18d_iii differential hstl 18 class iii ns hstl15_i hstl_15 class i ns
3-19 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet hstl15_ii hstl_15 class ii ns hstl15_iii hstl_15 class iii ns hstl15d_i differential hstl 15 class i ns hstl15d_iii differential hstl 15 class iii ns sstl33_i sstl_3 class i ns sstl33_ii sstl_3 class ii ns sstl33d_i differential sstl_3 class i ns sstl33d_ii differential sstl_3 class ii ns sstl25_i sstl_2 class i ns sstl25_ii sstl_2 class ii ns sstl25d_i differential sstl_2 class i ns sstl25d_ii differential sstl_2 class ii ns sstl18_i sstl_1.8 class i ns sstl18d_i differential sstl_1.8 class i ns l vttl33_4ma lvttl 4ma drive ns l vttl33_8ma lvttl 8ma drive ns l vttl33_12ma lvttl 12ma drive ns l vttl33_16ma lvttl 16ma drive ns l vttl33_20ma lvttl 20ma drive ns l vcmos33_4ma lvcmos 3.3 4ma drive ns l vcmos33_8ma lvcmos 3.3 8ma drive ns l vcmos33_12ma lvcmos 3.3 12ma drive ns l vcmos33_16ma lvcmos 3.3 16ma drive ns l vcmos33_20ma lvcmos 3.3 20ma drive ns l vcmos25_4ma lvcmos 2.5 4ma drive ns l vcmos25_8ma lvcmos 2.5 8ma drive ns l vcmos25_12ma lvcmos 2.5 12ma drive 0.00 0.00 0.00 ns l vcmos25_16ma lvcmos 2.5 16ma drive ns l vcmos25_20ma lvcmos 2.5 20ma drive ns l vcmos18_4ma lvcmos 1.8 4ma drive ns l vcmos18_8ma lvcmos 1.8 8ma drive ns l vcmos18_12ma lvcmos 1.8 12ma drive ns l vcmos18_16ma lvcmos 1.8 16ma drive ns l vcmos15_4ma lvcmos 1.5 4ma drive ns l vcmos15_8ma lvcmos 1.5 8ma drive ns l vcmos12_2ma lvcmos 1.2 2ma drive ns l vcmos12_6ma lvcmos 1.2 6ma drive ns l vcmos12_4ma lvcmos 1.2 4ma drive ns pci33 pci33 ns 1. timing adders are characterized but not tested on every device. latticeecp/ec family timing adders 1 (continued) over recommended operating conditions buffer type description -5 -4 -3 units
3-20 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet sysclock pll timing over recommended operating conditions p arameter descriptions conditions min. max. units f in input clock frequency (clki, clkfb) 33 420 mhz f out output clock frequency (clkop, clkos) 33 420 mhz f out2 k-divider output frequency (clkok) 0.258 210 mhz f vco pll vco frequency 420 840 mhz f pfd phase detector input frequency 33 ? mhz ac characteristics t dt output clock duty cycle default duty cycle selected 45 55 % t opjit output clock period jitter f out 100mhz ? +/- 100 ps f out < 100mhz ? 0.02 uipp t sk input clock to output clock skew divider ratio = integer ? +/- 200 ps t w output clock pulse width at 90% or 10% 1 ? ns t lock 1 pll lock-in time ? 150 us t pa programmable delay unit 100 400 ps t r /t f input clock rise/fall time 10% to 90% ? 1 ns t ipjit input clock period jitter ? +/- 200 ps t hi input clock high time 90% to 90% 0.5 ? ns t lo input clock low time 10% to 10% 0.5 ? ns 1. output clock is valid after t lock for pll reset and dynamic delay adjustment.
3-21 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec sysconfig port timing speci cations over recommended operating conditions p arameter description min. typ. max. units sysconfig byte data flow t sucbdi byte d[0:7] setup time to cclk 12 ? ns t hcbdi byte d[0:7] hold time to cclk 0 ? ns t codo clock to dout in flowthrough mode ? ns t sucs cs[0:1] setup time to cclk 12 ? ns t hcs cs[0:1] hold time to cclk 0 ? ns t suwd write signal setup time to cclk ? ns t hwd write signal hold time to cclk ? ns t dcb cclk to busy delay time ? 12 ns t cord clock to out for read data ? ns sysconfig byte slave clocking t bsch byte slave clock minimum high pulse 6 ? ns t bscl byte slave clock minimum low pulse 6 ? ns t bscyc byte slave clock cycle time 12 ? ns t suscdi din setup time to cclk slave mode 5 ? ns t hscdi din hold time to cclk slave mode 0 ? ns t codo clock to dout in flowthrough mode ? 12 ns sysconfig serial (bit) data flow t sumcdi din setup time to cclk master mode 5 ? ns t hmcdi din hold time to cclk master mode 0 ? ns sysconfig serial slave clocking t ssch serial slave clock minimum high pulse 6 ? ns t sscl serial slave clock minimum low pulse 6 ? ns sysconfig por, initialization and wake up t icfg initialization time of internal config circuit ? 5 ms t vmc time from t icfg to valid master clock ? 5 us t prgmrj program pin pulse rejection ? 10 ns t prgm low time to start con guration 25 ? ns t dinit init delay time 25 ? ns t dppinit delay time from program low to init low ? ns t dinitd delay time from program low to done low ? 37 ns t iodiss user i/o disable ? ns t ioenss user i/o enabled time from goe being released during wake-up ? ns t mwc additional wake master clock signals after done pin high ? 128 typical cycle sysconfig spi port t cfgx init high to clock low ? 80 ns t csspi init high to csspin low ? 2 ns t cscclk clock low to csspin low ? 0 ns t socdo clock low to output valid ? 15 ns t sosu data setup time 5 ? ns t soe csspin active setup time 0 ? ns t cspid csspin low to first clock edge setup time 400 ? ns
3-22 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec sysconfig port timing speci cations over recommended operating conditions clock mode min. typ. max. units master clock 5mhz 3.78 5.4 7.02 mhz 10mhz 7 10 13 mhz 15mhz 10.5 15 19.5 mhz 20mhz 14 20 26 mhz 25mhz 18.2 26 33.8 mhz 30mhz 21 30 39 mhz 35mhz 23.8 34 44.2 mhz 40mhz 28.7 41 53.3 mhz 45mhz 31.5 45 58.5 mhz 50mhz 35.7 51 66.3 mhz 55mhz 38.5 55 71.5 mhz 60mhz 42 60 78 mhz duty cycle 40 ? 60 %
3-23 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet jtag port timing speci cations over recommended operating conditions symbol parameter min. max. units f max tck clock frequency ? 25 mhz t btcp tck [bscan] clock pulse width 40 ? ns t btcph tck [bscan] clock pulse width high 20 ? ns t btcpl tck [bscan] clock pulse width low 20 ? ns t bts tck [bscan] setup time 8 ? ns t bth tck [bscan] hold time 10 ? ns t btrf tck [bscan] rise/fall time 50 ? mv/ns t btco t ap controller falling edge of clock to valid output ? 10 ns t btcodis t ap controller falling edge of clock to valid disable ? 10 ns t btcoen t ap controller falling edge of clock to valid enalbe ? 10 ns t btcrs bscan test capture register setup time 8 ? ns t btcrh bscan test capture register hold time 10 ? ns t b utco bscan test update register, falling edge of clock to valid output ? 25 ns t btuodis bscan test update register, falling edge of clock to valid disable ? 25 ns t btupoen bscan test update register, falling edge of clock to valid enable ? 25 ns
3-24 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet switching test conditions figure 3-12 shows the output test load that is used for ac testing. the speci c values for resistance, capacitance, v oltage, and other test conditions are shown in figure 3-5. figure 3-12. output test load, lvttl and lvcmos standards ta b le 3-5. test fixture required components, non-terminated interfaces t est condition r 1 c l timing ref. v t l vttl and other lvcmos settings (l -> h, h -> l) 0pf l vcmos 3.3 = 1.5v ? l vcmos 2.5 = v ccio /2 ? l vcmos 1.8 = v ccio /2 ? l vcmos 1.5 = v ccio /2 ? l vcmos 1.2 = v ccio /2 ? l vcmos 2.5 i/o (z -> h) 188 0pf v ccio /2 v ol l vcmos 2.5 i/o (z -> l) v ccio /2 v oh l vcmos 2.5 i/o (h -> z) v oh - 0.15 v ol l vcmos 2.5 i/o (l -> z) v ol + 0.15 v oh note: output test conditions for all other interfaces are determined by the respective standards. dut v t r1 cl* test point *cl includes test fixture and probe capacitance
www.latticesemi.com 4-1 pinout information_01 j une 2004 advance data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. signal descriptions signal name i/o descriptions general purpose p[edge] [row/column number*]_[a/b] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pic exists. when edge is t (top) or (bottom), only need to specify row number. when edge is l (left) or r (right), only need to specify col- umn number. [a/b] indicates the pio within the pic to which the pad is connected. some of these user-programmable pins are shared with special function pins. these pin when not used as special purpose pins can be programmed as i/os for user logic. during con guration the user-programmable i/os are tri-stated with an inter- nal pull-up resistor enabled. if any pin is not used (or not bonded to a pack- age pin), it is also tri-stated with an internal pull-up resistor enabled after con guration. gsrn i global reset signal (active low). any i/o pin can be gsrn. nc ? no connect. gnd ? ground. dedicated pins. v cc ?p ow er supply pins for core logic. dedicated pins. v ccaux ? a uxiliary power supply pin. it powers all the differential and referenced input b uffers. dedicated pins. v cciox ?p ow er supply pins for i/o bank x. dedicated pins. v ref1(x), v ref2(x) ? reference supply pins for i/o bank x. pre-determined pins in each bank are as assigned v ref inputs. when not used, they may be used as i/o pins. xres ? 10k ohm +/-1% resistor must be connected between this pad and ground. pll and clock functions (used as user programmable i/o pins when not in use for pll or clock pins) [loc][num]_pll[t, c]_in_a i reference clock (pll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_pll[t, c]_fb_a i optional feedback (pll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. pclk[t, c]_[n:0]_[3:0] i primary clock pads, t = true and c = complement, n per side, indexed by bank and 0,1,2,3 within bank. [loc]dqs[num] i dqs input pads: t (top), r (right), b (bottom), l (left), dqs, num = ball function number. any pad can be con gured to be output. t est and programming (dedicated pins) tms i t est mode select input, used to control the 1149.1 state machine. pull-up is enabled during con guration. tck i t est clock input pin, used to clock the 1149.1 state machine. no pull-up enabled. latticeecp/ec family data sheet pinout information
4-2 pinout information lattice semiconductor latticeecp/ec family data sheet tdi i t est data in pin. used to load data into device using 1149.1 state machine. after power-up, this tap port can be activated for con guration by sending appropriate command. (note: once a con guration port is selected it is locked. another con guration port cannot be selected until the power-up sequence). pull-up is enabled during con guration. tdo o output pin. test data out pin used to shift data out of device using 1149.1. v ccj ?v ccj - the power supply pin for jtag test access port. con guration pads (used during sysconfig) cfg[2:0] i mode pins used to specify con guration modes values latched on rising edge of initn. during con guration, a pull-up is enabled. these are dedicated pins. initn i/o open drain pin. indicates the fpga is ready to be con gured. during con g- uration, a pull-up is enabled. it is a dedicated pin. programn i initiates con guration sequence when asserted low. this pin always has an active pull-up. this is a dedicated pin. done i/o open drain pin. indicates that the con guration sequence is complete, and the startup sequence is in progress. this is a dedicated pin. cclk i/o con guration clock for con guring an fpga in sysconfig mode. b usy i/o generally not used. csn i sysconfig chip select (active low). during con guration, a pull-up is enabled. cs1n i sysconfig chip select (active low). during con guration, a pull-up is enabled. writen i write data on parallel port (active low). d[7:0] i/o sysconfig port data i/o. dout, cson o output for serial con guration data (rising edge of cclk) when using sysconfig port. di i input for serial con guration data (clocked with cclk) when using syscon- fig port. during con guration, a pull-up is enabled. signal descriptions (cont.) signal name i/o descriptions
4-3 pinout information lattice semiconductor latticeecp/ec family data sheet lfec20/lfecp20 pin information summary package pin type 484 fpbga 672 fpbga single ended user i/o 360 400 differential pair user i/o 180 200 con guration dedicated 12 12 muxed 56 56 ta p 5 5 dedicated (total without supplies) v cc 20 32 v ccaux 12 20 v ccio bank0 4 6 bank1 4 6 bank2 4 6 bank3 4 6 bank4 4 6 bank5 4 6 bank6 4 6 bank7 4 6 gnd 44 63 nc 3 96 single ended/ differential i/o per bank bank0 48 64 bank1 48 48 bank2 40 40 bank3 44 48 bank4 48 48 bank5 48 64 bank6 44 48 bank7 40 40 v ccj 11 note: during con guration the user-programmable i/os are tri-stated with an inter- nal pull-up resistor enabled. if any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after con guration.
4-4 pinout information lattice semiconductor latticeecp/ec family data sheet lfec20/lfecp20 power supply and nc connections signals 484 fpbga 672 fpbga vcc j6, j7, j16, j17, k6, k7, k16, k17, l6, l17, m6, m17, n6, n7, n16, n17, p6, p7, p16, p17 h8, h9, h10, h11, h16, h17, h18, h19, j9, j18, k8, k19, l8, l19, m19, n7, r7, r20, t19, u8, u19, v8, v18, v9, w8, w9, w10, w11, w16, w17, w18, w19 vccio0 g11, h9, h10, h11 h12, h13, j10, j11, j12, j13 vccio1 g12, h12, h13, h14 h14, h15, j14, j15, j16, j17 vccio2 j15, k15, l15, l16 k17, k18, l18, m18, n18, n19 vccio3 m15, m16, n15, p15 p18, p19, r18, r19, t18, u18 vccio4 r12, r13, r14, t12 v14, v15, v16, v17, w14, w15 vccio5 r9, r10, r11, t11 v10, v11, v12, v13, w12, w13 vccio6 m7, m8, n8, p8 p8, p9, r8, r9, t9, u9 vccio7 j8, k8, l7, l8 k9, l9, m8, m9, n8, n9 vccj u2 u6 vccaux g7, g8, g15, g16, h7, h16, r7, r16, t7, t8, t15, t16 g13,h7, h20, j8, j19, k7, l20, m7, m20, n20, p7, p20, t7, t8, t20, v7, v19, w20, y7, y13 gnd a1, a22, ab1, ab22, h8, h15, j9, j10, j11, j12, j13, j14, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n9, n10, n11, n12, n13, n14, p9, p10, p11, p12, p13, p14, r8, r15 k10, k11, k12, k13, k14, k15, k16, l10, l11, l12, l13, l14, l15, l16, l17, m10, m11, m12, m13, m14, m15, m16, m17, n10, n11, n12, n13, n14, n15, n16, n17, p10, p11, p12, p13, p14, p15, p16, p17, r10, r11, r12, r13, r14, r15, r16, r17, t10, t11, t12, t13, t14, t15, t16, t17, u10, u11, u12, u13, u14, u15, u16, u17 nc a2, a21, ab2 a25, b2, b23, b24, b25, b26, c2, c3, c19, c20, c21, c22, c23, c24, d3, d5, d20, d21, d22, d24, e5, e19, e21, e22, e24, e25, e26, f4, f5, f20, f22, f23, f24, f26, g5, g20, g26, h2, h3, h5, h6, h22, j2, j3, j7, j21, j22, j23, w5, w7, y5, y6, y19, y20, y21, y22, y23, y24, aa2, aa3, aa4, aa5, aa21, aa22, aa23, aa24, ab3, ab5, ab19, ab20, ab21, ab22, ab23, ab24, ac2, ac3, ac19, ac20, ac21, a c22, ad1, ad2, ad3, ad19, ad20, ad21, ad22, ad23, ad24, ad25, ad26, ae1, ae24, ae25, ae26, af25
4-5 pinout information lattice semiconductor latticeecp/ec family data sheet lfec20/lfecp20 logic signal connections: 484 & 672 fpbga ball function bank lvds dual function 484 fpbga 672 fpbga pl2a 7 t vref2_7 d4 e3 pl2b 7 c vref1_7 e4 e4 pl3a 7 t c3 b1 pl3b 7 c b2 c1 pl4a 7 t e5 f3 pl4b 7 c f5 g3 pl5a 7 t d3 d2 pl5b 7 c c2 e2 pl6a 7 t ldqs6 f4 d1 pl6b 7 c g4 e1 pl7a 7 t e3 f2 pl7b 7 c d2 g2 pl8a 7 t lum0_pllt_in_a b1 f6 pl8b 7 c lum0_pllc_in_a c1 g6 pl9a 7 t lum0_pllt_fb_a f3 h4 pl9b 7 c lum0_pllc_fb_a e2 g4 pl11a 7 t g5 j4 pl11b 7 c h6 j5 pl12a 7 t g3 k4 pl12b 7 c h4 k5 pl13a 7 t j5 j6 pl13b 7 c h5 k6 pl14a 7 t f2 f1 pl14b 7 c f1 g1 pl15a 7 t e1 h1 pl15b 7 c d1 j1 pl16a 7 t h3 k2 pl16b 7 c g2 k1 pl17a 7 t h2 k3 pl17b 7 c g1 l3 pl18a 7 t j4 l2 pl18b 7 c j3 l1 pl19a 7 t ldqs19 j2 m3 pl19b 7 c h1 m4 pl20a 7 t k4 m1 pl20b 7 c k5 m2 pl21a 7 t k3 l4 pl21b 7 c k2 l5 pl22a 7 t pclkt7_0 j1 n2 pl22b 7 c pclkc7_0 k1 n1 xres 6 l3 n3 pl24a 6 t l4 p1 pl24b 6 c l5 p2
4-6 pinout information lattice semiconductor latticeecp/ec family data sheet pl25a 6 t l2 l7 pl25b 6 c l1 l6 pl26a 6 t m4 n4 pl26b 6 c m5 n5 pl27a 6 t m1 r1 pl27b 6 c m2 r2 pl28a 6 t ldqs28 n3 p4 pl28b 6 c m3 p3 pl29a 6 t n5 m5 pl29b 6 c n4 m6 pl30a 6 t n1 t1 pl30b 6 c n2 t2 pl31a 6 t p1 r4 pl31b 6 c p2 r3 pl32a 6 t r6 n6 pl32b 6 c p5 p5 pl33a 6 t p3 p6 pl33b 6 c p4 r5 pl34a 6 t r1 u1 pl34b 6 c r2 u2 pl35a 6 t r5 t3 pl35b 6 c r4 t4 pl36a 6 t ldqs36 t1 r6 pl36b 6 c t2 t5 pl37a 6 t r3 t6 pl37b 6 c t3 u5 pl38a 6 t u3 pl38b 6 c u4 pl39a 6 t v1 pl39b 6 c v2 tck 6 t5 u7 tdi 6 u5 v4 tms 6 t4 v5 tdo 6 u1 v3 vccj 6 u2 u6 pl41a 6 t llm0_pllt_in_a v1 w1 pl41b 6 c llm0_pllc_in_a v2 w2 pl42a 6 t llm0_pllt_fb_a u3 v6 pl42b 6 c llm0_pllc_fb_a v3 w6 pl43a 6 t u4 y1 pl43b 6 c v5 y2 pl44a 6 t w1 w3 pl44b 6 c w2 w4 pl45a 6 t ldqs45 y1 aa1 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
4-7 pinout information lattice semiconductor latticeecp/ec family data sheet pl45b 6 c y2 ab1 pl46a 6 t aa1 y4 pl46b 6 c aa2 y3 pl47a 6 t w4 ac1 pl47b 6 c v4 ab2 pl48a 6 t vref1_6 w3 ab4 pl48b 6 c vref2_6 y3 ac4 pb2a 5 t ab6 pb2b 5 c aa6 pb3a 5 t ac7 pb3b 5 c y8 pb4a 5 t ab7 pb4b 5 c aa7 pb5a 5 t ac6 pb5b 5 c ac5 pb6a 5 t bdqs6 ab8 pb6b 5 c ac8 pb7a 5 t ae2 pb7b 5 c aa8 pb8a 5 t af2 pb8b 5 c y9 pb9a 5 t ad5 pb9b 5 c ad4 pb10a 5 t v7 ad8 pb10b 5 c t6 ac9 pb11a 5 t v8 ae3 pb11b 5 c u7 ab9 pb12a 5 t w5 af3 pb12b 5 c u6 ad9 pb13a 5 t aa3 ae4 pb13b 5 c ab3 af4 pb14a 5 t bdqs14 y6 ae5 pb14b 5 c v6 aa9 pb15a 5 t aa5 af5 pb15b 5 c w6 y10 pb16a 5 t y5 ad6 pb16b 5 c y4 ac10 pb17a 5 t aa4 af6 pb17b 5 c ab4 ae6 pb18a 5 t y7 af7 pb18b 5 c w8 ab10 pb19a 5 t w7 ae7 pb19b 5 c u8 ad10 pb20a 5 t w9 ad7 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
4-8 pinout information lattice semiconductor latticeecp/ec family data sheet pb20b 5 c u9 aa10 pb21a 5 t y8 af8 pb21b 5 c y9 af9 pb22a 5 t bdqs22 v9 ad11 pb22b 5 c t9 y11 pb23a 5 t w10 ae8 pb23b 5 c u10 ac11 pb24a 5 t v10 af10 pb24b 5 c t10 ab11 pb25a 5 t aa6 ae10 pb25b 5 c ab5 ae9 pb26a 5 t aa8 aa11 pb26b 5 c aa7 y12 pb27a 5 t ab6 ae11 pb27b 5 c ab7 af11 pb28a 5 t y10 af12 pb28b 5 c w11 ae12 pb29a 5 t ab8 ad12 pb29b 5 c ab9 ac12 pb30a 5 t bdqs30 aa10 aa12 pb30b 5 c aa9 ab12 pb31a 5 t y11 ae13 pb31b 5 c aa11 af13 pb32a 5 t vref2_5 v11 ad13 pb32b 5 c vref1_5 v12 ac13 pb33a 5 t pclkt5_0 ab10 af14 pb33b 5 c pclkc5_0 ab11 ae14 pb34a 4 t writen y12 aa13 pb34b 4 c cs1n u11 ab13 pb35a 4 t vref1_4 w12 ad14 pb35b 4 c csn u12 aa14 pb36a 4 t vref2_4 w13 ac14 pb36b 4 c d7 u13 ab14 pb37a 4 t d5 aa12 af15 pb37b 4 c d6 ab12 ae15 pb38a 4 t bdqs38 t13 ad15 pb38b 4 c d4 v13 ac15 pb39a 4 t w14 af16 pb39b 4 c d3 u14 y14 pb40a 4 t y13 ae16 pb40b 4 c d2 v14 ab15 pb41a 4 t aa13 af17 pb41b 4 c d1 ab13 ae17 pb42a 4 t aa14 y15 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
4-9 pinout information lattice semiconductor latticeecp/ec family data sheet pb42b 4 c y14 aa15 pb43a 4 t y15 ad17 pb43b 4 c w15 y16 pb44a 4 t v15 ad18 pb44b 4 c t14 ac16 pb45a 4 t ab14 ae18 pb45b 4 c ab15 af18 pb46a 4 t bdqs46 ab16 ad16 pb46b 4 c aa15 ab16 pb47a 4 t ab17 af19 pb47b 4 c aa16 aa16 pb48a 4 t ab18 aa17 pb48b 4 c aa17 y17 pb49a 4 t ab19 af21 pb49b 4 c aa18 af20 pb50a 4 t w16 ae21 pb50b 4 c u15 ac17 pb51a 4 t v16 af22 pb51b 4 c u16 ab17 pb52a 4 t y17 ae22 pb52b 4 c v17 aa18 pb53a 4 t ab20 ae19 pb53b 4 c aa19 ae20 pb54a 4 t bdqs54 y16 aa19 pb54b 4 c w17 y18 pb55a 4 t aa20 af23 pb55b 4 c y19 aa20 pb56a 4 t y18 ac18 pb56b 4 c w18 ab18 pb57a 4 t t17 af24 pb57b 4 c u17 ae23 pr48b 3 c vref2_3 w20 ac23 pr48a 3 t vref1_3 y20 ac24 pr47b 3 c aa21 ac25 pr47a 3 t ab21 ac26 pr46b 3 c w19 ab25 pr46a 3 t v19 aa25 pr45b 3 c y21 ab26 pr45a 3 t rdqs45 aa22 aa26 pr44b 3 c rlm0_pllc_in_a v20 w23 pr44a 3 t rlm0_pllt_in_a u20 w24 pr43b 3 c rlm0_pllc_fb_a w21 w22 pr43a 3 t rlm0_pllt_fb_a y22 w21 pr42b 3 c di v21 y25 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
4-10 pinout information lattice semiconductor latticeecp/ec family data sheet pr42a 3 t dout/cson w22 y26 pr41b 3 c busy u21 w25 pr41a 3 t d0 v22 w26 cfg2 3 t19 v24 cfg1 3 u19 v21 cfg0 3 u18 v23 programn 3 v18 v22 cclk 3 t20 v20 initn 3 t21 v25 done 3 r20 u20 pr39b 3 c v26 pr39a 3 t u26 pr38b 3 c u24 pr38a 3 t u25 pr37b 3 c t18 u23 pr37a 3 t r17 u22 pr36b 3 c r19 u21 pr36a 3 t rdqs36 r18 t21 pr35b 3 c u22 t25 pr35a 3 t t22 t26 pr34b 3 c r21 t22 pr34a 3 t r22 t23 pr33b 3 c p20 t24 pr33a 3 t n20 r23 pr32b 3 c p19 r25 pr32a 3 t p18 r24 pr31b 3 c p21 r26 pr31a 3 t p22 p26 pr30b 3 c n21 r21 pr30a 3 t n22 r22 pr29b 3 c n19 p25 pr29a 3 t n18 p24 pr28b 3 c m21 p23 pr28a 3 t rdqs28 l20 p22 pr27b 3 c l21 n26 pr27a 3 t m20 m26 pr26b 3 c m18 n21 pr26a 3 t m19 p21 pr25b 3 c m22 n23 pr25a 3 t l22 n22 pr24b 3 c k22 n25 pr24a 3 t k21 n24 pr22b 2 c pclkc2_0 j22 l26 pr22a 2 t pclkt2_0 j21 k26 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
4-11 pinout information lattice semiconductor latticeecp/ec family data sheet pr21b 2 c h22 m22 pr21a 2 t h21 m23 pr20b 2 c l19 m25 pr20a 2 t l18 m24 pr19b 2 c k20 m21 pr19a 2 t rdqs19 j20 l21 pr18b 2 c k19 l22 pr18a 2 t k18 l23 pr17b 2 c g22 l25 pr17a 2 t f22 l24 pr16b 2 c f21 k25 pr16a 2 t e22 j25 pr15b 2 c e21 j26 pr15a 2 t d22 h26 pr14b 2 c g21 h25 pr14a 2 t g20 j24 pr13b 2 c j18 k21 pr13a 2 t h19 k22 pr12b 2 c j19 k20 pr12a 2 t h20 j20 pr11b 2 c h17 k23 pr11a 2 t h18 k24 pr9b 2 c rum0_pllc_fb_ a d21 f25 pr9a 2 t rum0_pllt_fb_a c22 g25 pr8b 2 c rum0_pllc_in_a g19 h23 pr8a 2 t rum0_pllt_in_a g18 h24 pr7b 2 c f20 h21 pr7a 2 t f19 g21 pr6b 2 c e20 d26 pr6a 2 t rdqs6 d20 d25 pr5b 2 c c21 f21 pr5a 2 t c20 g22 pr4b 2 c f18 g24 pr4a 2 t e18 g23 pr3b 2 c b22 c26 pr3a 2 t b21 c25 pr2b 2 c vref1_2 e19 e23 pr2a 2 t vref2_2 d19 d23 pt57b 1 c g17 a24 pt57a 1 t f17 a23 pt56b 1 c d18 e18 pt56a 1 t c18 d19 pt55b 1 c c19 f19 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
4-12 pinout information lattice semiconductor latticeecp/ec family data sheet pt55a 1 t b20 b22 pt54b 1 c d17 g19 pt54a 1 t tdqs54 c16 b21 pt53b 1 c b19 d18 pt53a 1 t a20 c18 pt52b 1 c e17 f18 pt52a 1 t c17 a22 pt51b 1 c f16 g18 pt51a 1 t e16 a21 pt50b 1 c f15 e17 pt50a 1 t d16 b17 pt49b 1 c b18 c17 pt49a 1 t a19 d17 pt48b 1 c b17 f17 pt48a 1 t a18 e20 pt47b 1 c b16 g17 pt47a 1 t a17 b20 pt46b 1 c b15 e16 pt46a 1 t tdqs46 a16 a20 pt45b 1 c a15 a19 pt45a 1 t a14 b19 pt44b 1 c g14 d16 pt44a 1 t e15 c16 pt43b 1 c d15 f16 pt43a 1 t c15 a18 pt42b 1 c c14 g16 pt42a 1 t b14 b18 pt41b 1 c a13 a17 pt41a 1 t b13 a16 pt40b 1 c e14 d15 pt40a 1 t c13 b16 pt39b 1 c f14 e15 pt39a 1 t d14 c15 pt38b 1 c e13 f15 pt38a 1 t tdqs38 g13 g15 pt37b 1 c a12 b15 pt37a 1 t b12 a15 pt36b 1 c f13 e14 pt36a 1 t d13 g14 pt35b 1 c vref2_1 f12 d14 pt35a 1 t vref1_1 d12 e13 pt34b 1 c f11 f14 pt34a 1 t c12 c14 pt33b 0 c pclkc0_0 a11 b14 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
4-13 pinout information lattice semiconductor latticeecp/ec family data sheet pt33a 0 t pclkt0_0 a10 a14 pt32b 0 c vref1_0 e12 d13 pt32a 0 t vref2_0 e11 c13 pt31b 0 c b11 a13 pt31a 0 t c11 b13 pt30b 0 c b9 f13 pt30a 0 t tdqs30 b10 f12 pt29b 0 c a9 a12 pt29a 0 t a8 b12 pt28b 0 c d11 a11 pt28a 0 t c10 b11 pt27b 0 c a7 d12 pt27a 0 t a6 c12 pt26b 0 c b7 b10 pt26a 0 t b8 a10 pt25b 0 c a5 g12 pt25a 0 t b6 a9 pt24b 0 c g10 e12 pt24a 0 t e10 b9 pt23b 0 c f10 f11 pt23a 0 t d10 a8 pt22b 0 c g9 d11 pt22a 0 t tdqs22 e9 c11 pt21b 0 c c9 b8 pt21a 0 t c8 b7 pt20b 0 c f9 e11 pt20a 0 t d9 a7 pt19b 0 c f8 g11 pt19a 0 t d7 c7 pt18b 0 c d8 g10 pt18a 0 t c7 c6 pt17b 0 c a4 c10 pt17a 0 t b4 d10 pt16b 0 c c4 f10 pt16a 0 t c5 a6 pt15b 0 c d6 e10 pt15a 0 t b5 c9 pt14b 0 c e6 g9 pt14a 0 t tdqs14 c6 d9 pt13b 0 c a3 a5 pt13a 0 t b3 a4 pt12b 0 c f6 f9 pt12a 0 t d5 b6 pt11b 0 c f7 e9 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
4-14 pinout information lattice semiconductor latticeecp/ec family data sheet pt11a 0 t e8 c8 pt10b 0 c g6 g8 pt10a 0 t e7 b5 pt9b 0 c a3 pt9a 0 t a2 pt8b 0 c f8 pt8a 0 t b4 pt7b 0 c e8 pt7a 0 t b3 pt6b 0 c d8 pt6a 0 t tdqs6 g7 pt5b 0 c c4 pt5a 0 t c5 pt4b 0 c e7 pt4a 0 t d4 pt3b 0 c f7 pt3a 0 t d6 pt2b 0 c d7 pt2a 0 t e6 lfec20/lfecp20 logic signal connections: 484 & 672 fpbga (cont.) ball function bank lvds dual function 484 fpbga 672 fpbga
www.latticesemi.com 5-1 order info_01 j une 2004 advance data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. pa rt number description ordering information latticeec commercial pa rt number i/os grade package pins temp. luts lfec1e-3 q208c 112 -3 pqfp 208 com 1.5k lfec1e-4 q208c 112 -4 pqfp 208 com 1.5k lfec1e-5 q208c 112 -5 pqfp 208 com 1.5k lfec1e-3 t144c 97 -3 tqfp 144 com 1.5k lfec1e-4 t144c 97 -4 tqfp 144 com 1.5k lfec1e-5 t144c 97 -5 tqfp 144 com 1.5k lfec1e-3 t100c 65 -3 tqfp 100 com 1.5k lfec1e-4 t100c 65 -4 tqfp 100 com 1.5k lfec1e-5 t100c 65 -5 tqfp 100 com 1.5k pa rt number i/os grade package pins temp. luts lfec3e-3 f256c 160 -3 fpbga 256 com 3.1k lfec3e-4 f256c 160 -4 fpbga 256 com 3.1k lfec3e-5 f256c 160 -5 fpbga 256 com 3.1k lfec3e-3 q208c 145 -3 pqfp 208 com 3.1k lfec3e-4 q208c 145 -4 pqfp 208 com 3.1k lfec3e-5 q208c 145 -5 pqfp 208 com 3.1k lfec3e-3 t144c 97 -3 tqfp 144 com 3.1k lfxxx xx ? x ? x xxxxxx x grade c = commercial i = industrial logic capacity 1.5k luts = 1* 3k luts = 3* 6k luts = 6 10k luts = 10 15k luts = 15 20k luts = 20 40k luts = 40 note: parts dual marked per table below. *not available in the latticeecp family. supply voltage e = 1.2v speed 3 = slowest 4 5 = fastest package t100 = 100-pin tqfp* t144 = 144-pin tqfp q208 = 208-pin pqfp f256 = 256-ball fpbga f484 = 484-ball fpbga f672 = 672-ball fpbga f900 = 900-ball fpbga device family lattice ec (fpga) lattice ecp (ec fpga + dsp blocks) latticeecp/ec family data sheet ordering information
5-2 ordering information lattice semiconductor latticeecp/ec family data sheet lfec3e-4 t144c 97 -4 tqfp 144 com 3.1k lfec3e-5 t144c 97 -5 tqfp 144 com 3.1k lfec3e-3 t100c 65 -3 tqfp 100 com 3.1k lfec3e-4 t100c 65 -4 tqfp 100 com 3.1k lfec3e-5 t100c 65 -5 tqfp 100 com 3.1k lfec6e-3 f484c 224 -3 fpbga 484 com 6.1k lfec6e-4 f484c 224 -4 fpbga 484 com 6.1k lfec6e-5 f484c 224 -5 fpbga 484 com 6.1k lfec6e-3 f256c 192 -3 fpbga 256 com 6.1k lfec6e-4 f256c 192 -4 fpbga 256 com 6.1k lfec6e-5 f256c 192 -5 fpbga 256 com 6.1k lfec6e-3 q208c 145 -3 pqfp 208 com 6.1k lfec6e-4 q208c 145 -4 pqfp 208 com 6.1k lfec6e-5 q208c 145 -5 pqfp 208 com 6.1k lfec6e-3 t144c 97 -3 tqfp 144 com 6.1k lfec6e-4 t144c 97 -4 tqfp 144 com 6.1k lfec6e-5 t144c 97 -5 tqfp 144 com 6.1k pa rt number i/os grade package pins temp. luts lfec10e-3 f484c 288 -3 fpbga 484 com 10.2k lfec10e-4 f484c 288 -4 fpbga 484 com 10.2k lfec10e-5 f484c 288 -5 fpbga 484 com 10.2k lfec10e-3 f256c 192 -3 fpbga 256 com 10.2k lfec10e-4 f256c 192 -4 fpbga 256 com 10.2k lfec10e-5 f256c 192 -5 fpbga 256 com 10.2k lfec10e-3 q208c 145 -3 pqfp 208 com 10.2k lfec10e-4 q208c 145 -4 pqfp 208 com 10.2k lfec10e-5 q208c 145 -5 pqfp 208 com 10.2k pa rt number i/os grade package pins temp. luts lfec15e-3 f484c 352 -3 fpbga 484 com 15.3k lfec15e-4 f484c 352 -4 fpbga 484 com 15.3k lfec15e-5 f484c 352 -5 fpbga 484 com 15.3k lfec15e-3 f256c 192 -3 fpbga 256 com 15.3k lfec15e-4 f256c 192 -4 fpbga 256 com 15.3k lfec15e-5 f256c 192 -5 fpbga 256 com 15.3k pa rt number i/os grade package pins temp. luts lfec20e-3 f672c 400 -3 fpbga 672 com 19.7k lfec20e-4 f672c 400 -4 fpbga 672 com 19.7k lfec20e-5 f672c 400 -5 fpbga 672 com 19.7k lfec20e-3 f484c 360 -3 fpbga 484 com 19.7k lfec20e-4 f484c 360 -4 fpbga 484 com 19.7k lfec20e-5 f484c 360 -5 fpbga 484 com 19.7k latticeec commercial (continued) pa rt number i/os grade package pins temp. luts
5-3 ordering information lattice semiconductor latticeecp/ec family data sheet pa rt number i/os grade package pins temp. luts lfec40e-3 f900c 576 -3 fpbga 900 com 40.9k lfec40e-4 f900c 576 -4 fpbga 900 com 40.9k lfec40e-5 f900c 576 -5 fpbga 900 com 40.9k lfec40e-3 f672c 496 -3 fpbga 672 com 40.9k lfec40e-4 f672c 496 -4 fpbga 672 com 40.9k lfec40e-5 f672c 496 -5 fpbga 672 com 40.9k latticeecp commercial pa rt number i/os grade package pins temp. luts lfecp6e-3 f484c 224 -3 fpbga 484 com 6.1k lfecp6e-4 f484c 224 -4 fpbga 484 com 6.1k lfecp6e-5 f484c 224 -5 fpbga 484 com 6.1k lfecp6e-3 f256c 192 -3 fpbga 256 com 6.1k lfecp6e-4 f256c 192 -4 fpbga 256 com 6.1k lfecp6e-5 f256c 192 -5 fpbga 256 com 6.1k lfecp6e-3 q208c 145 -3 pqfp 208 com 6.1k lfecp6e-4 q208c 145 -4 pqfp 208 com 6.1k lfecp6e-5 q208c 145 -5 pqfp 208 com 6.1k lfecp6e-3 t144c 97 -3 tqfp 144 com 6.1k lfecp6e-4 t144c 97 -4 tqfp 144 com 6.1k lfecp6e-5 t144c 97 -5 tqfp 144 com 6.1k pa rt number i/os grade package pins temp. luts lfecp10e-3 f484c 288 -3 fpbga 484 com 10.2k lfecp10e-4 f484c 288 -4 fpbga 484 com 10.2k lfecp10e-5 f484c 288 -5 fpbga 484 com 10.2k lfecp10e-3 f256c 192 -3 fpbga 256 com 10.2k lfecp10e-4 f256c 192 -4 fpbga 256 com 10.2k lfecp10e-5 f256c 192 -5 fpbga 256 com 10.2k lfecp10e-3 q208c 145 -3 pqfp 208 com 10.2k lfecp10e-4 q208c 145 -4 pqfp 208 com 10.2k lfecp10e-5 q208c 145 -5 pqfp 208 com 10.2k pa rt number i/os grade package pins temp. luts lfecp15e-3 f484c 352 -3 fpbga 484 com 15.3k lfecp15e-4 f484c 352 -4 fpbga 484 com 15.3k lfecp15e-5 f484c 352 -5 fpbga 484 com 15.3k lfecp15e-3 f256c 192 -3 fpbga 256 com 15.3k lfecp15e-4 f256c 192 -4 fpbga 256 com 15.3k lfecp15e-5 f256c 192 -5 fpbga 256 com 15.3k latticeec commercial (continued) pa rt number i/os grade package pins temp. luts
5-4 ordering information lattice semiconductor latticeecp/ec family data sheet pa rt number i/os grade package pins temp. luts lfecp20e-3 f676c 400 -3 fpbga 676 com 19.7k lfecp20e-4 f676c 400 -4 fpbga 676 com 19.7k lfecp20e-5 f676c 400 -5 fpbga 676 com 19.7k lfecp20e-3 f484c 360 -3 fpbga 484 com 19.7k lfecp20e-4 f484c 360 -4 fpbga 484 com 19.7k lfecp20e-5 f484c 360 -5 fpbga 484 com 19.7k pa rt number i/os grade package pins temp. luts lfecp40e-3 f896c 576 -3 fpbga 896 com 40.9k lfecp40e-4 f896c 576 -4 fpbga 896 com 40.9k lfecp40e-5 f896c 576 -5 fpbga 896 com 40.9k lfecp40e-3 f676c 496 -3 fpbga 676 com 40.9k lfecp40e-4 f676c 496 -4 fpbga 676 com 40.9k lfecp40e-5 f676c 496 -5 fpbga 676 com 40.9k latticeec industrial pa rt number i/os grade package pins temp. luts lfec1e-3 q208i 112 -3 pqfp 208 ind 1.5k lfec1e-4 q208i 112 -4 pqfp 208 ind 1.5k lfec1e-3 t144i 97 -3 tqfp 144 ind 1.5k lfec1e-4 t144i 97 -4 tqfp 144 ind 1.5k lfec1e-3 t100i 65 -3 tqfp 100 ind 1.5k lfec1e-4 t100i 65 -4 tqfp 100 ind 1.5k pa rt number i/os grade package pins temp. luts lfec3e-3 f256i 160 -3 fpbga 256 ind 3.1k lfec3e-4 f256i 160 -4 fpbga 256 ind 3.1k lfec3e-3 q208i 145 -3 pqfp 208 ind 3.1k lfec3e-4 q208i 145 -4 pqfp 208 ind 3.1k lfec3e-3 t144i 97 -3 tqfp 144 ind 3.1k lfec3e-4 t144i 97 -4 tqfp 144 ind 3.1k lfec3e-3 t100i 65 -3 tqfp 100 ind 3.1k lfec3e-4 t100i 65 -4 tqfp 100 ind 3.1k pa rt number i/os grade package pins temp. luts lfec6e-3 f484i 224 -3 fpbga 484 ind 6.1k lfec6e-4 f484i 224 -4 fpbga 484 ind 6.1k lfec6e-3 f256i 192 -3 fpbga 256 ind 6.1k lfec6e-4 f256i 192 -4 fpbga 256 ind 6.1k lfec6e-3 q208i 145 -3 pqfp 208 ind 6.1k lfec6e-4 q208i 145 -4 pqfp 208 ind 6.1k lfec6e-3 t144i 97 -3 tqfp 144 ind 6.1k latticeecp commercial (continued)
5-5 ordering information lattice semiconductor latticeecp/ec family data sheet lfec6e-4 t144i 97 -4 tqfp 144 ind 6.1k pa rt number i/os grade package pins temp. luts lfec10e-3 f484i 288 -3 fpbga 484 ind 10.2k lfec10e-4 f484i 288 -4 fpbga 484 ind 10.2k lfec10e-3 f256i 192 -3 fpbga 256 ind 10.2k lfec10e-4 f256i 192 -4 fpbga 256 ind 10.2k lfec10e-3 p208i 145 -3 pqfp 208 ind 10.2k lfec10e-4 p208i 145 -4 pqfp 208 ind 10.2k pa rt number i/os grade package pins temp. luts lfec15e-3 f484i 352 -3 fpbga 484 ind 15.3k lfec15e-4 f484i 352 -4 fpbga 484 ind 15.3k lfec15e-3 f256i 192 -3 fpbga 256 ind 15.3k lfec15e-4 f256i 192 -4 fpbga 256 ind 15.3k pa rt number i/os grade package pins temp. luts lfec20e-3 f672i 400 -3 fpbga 672 ind 19.7k lfec20e-4 f672i 400 -4 fpbga 672 ind 19.7k lfec20e-3 f484i 360 -3 fpbga 484 ind 19.7k lfec20e-4 f484i 360 -4 fpbga 484 ind 19.7k pa rt number i/os grade package pins temp. luts lfec40e-3 f900i 576 -3 fpbga 900 ind 40.9k lfec40e-4 f900i 576 -4 fpbga 900 ind 40.9k lfec40e-3 f672i 496 -3 fpbga 672 ind 40.9k lfec40e-4 f672i 496 -4 fpbga 672 ind 40.9k latticeecp industrial pa rt number i/os grade package pins temp. luts lfecp6e-3 f484i 224 -3 fpbga 484 ind 6.1k lfecp6e-4 f484i 224 -4 fpbga 484 ind 6.1k lfecp6e-3 f256i 192 -3 fpbga 256 ind 6.1k lfecp6e-4 f256i 192 -4 fpbga 256 ind 6.1k lfecp6e-3 q208i 145 -3 pqfp 208 ind 6.1k latticeec industrial (continued) pa rt number i/os grade package pins temp. luts lfec1e-3 q208i 112 -3 pqfp 208 ind 1.5k lfec1e-4 q208i 112 -4 pqfp 208 ind 1.5k lfec1e-3 t144i 97 -3 tqfp 144 ind 1.5k lfec1e-4 t144i 97 -4 tqfp 144 ind 1.5k lfec1e-3 t100i 65 -3 tqfp 100 ind 1.5k lfec1e-4 t100i 65 -4 tqfp 100 ind 1.5k pa rt number i/os grade package pins temp. luts
5-6 ordering information lattice semiconductor latticeecp/ec family data sheet lfecp6e-4 q208i 145 -4 pqfp 208 ind 6.1k lfecp6e-3 t144i 97 -3 tqfp 144 ind 6.1k lfecp6e-4 t144i 97 -4 tqfp 144 ind 6.1k pa rt number i/os grade package pins temp. luts lfecp10e-3 f484i 288 -3 fpbga 484 ind 10.2k lfecp10e-4 f484i 288 -4 fpbga 484 ind 10.2k lfecp10e-3 f256i 192 -3 fpbga 256 ind 10.2k lfecp10e-4 f256i 192 -4 fpbga 256 ind 10.2k lfecp10e-3 q208i 145 -3 pqfp 208 ind 10.2k lfecp10e-4 q208i 145 -4 pqfp 208 ind 10.2k pa rt number i/os grade package pins temp. luts lfecp15e-3 f484i 352 -3 fpbga 484 ind 15.3k lfecp15e-4 f484i 352 -4 fpbga 484 ind 15.3k lfecp15e-3 f256i 192 -3 fpbga 256 ind 15.3k lfecp15e-4 f256i 192 -4 fpbga 256 ind 15.3k pa rt number i/os grade package pins temp. luts lfecp20e-3 f676i 400 -3 fpbga 676 ind 19.7k lfecp20e-4 f676i 400 -4 fpbga 676 ind 19.7k lfecp20e-3 f484i 360 -3 fpbga 484 ind 19.7k lfecp20e-4 f484i 360 -4 fpbga 484 ind 19.7k pa rt number i/os grade package pins temp. luts lfecp40e-3 f896i 576 -3 fpbga 896 ind 40.9k lfecp40e-4 f896i 576 -4 fpbga 896 ind 40.9k lfecp40e-3 f676i 496 -3 fpbga 676 ind 40.9k lfecp40e-4 f676i 496 -4 fpbga 676 ind 40.9k latticeecp industrial (continued)
j une 2004 advance data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. www.latticesemi.com 6-1 further info_01 for further information a variety of technical notes for the latticeecp/ec family are available on the lattice web site at www .latticesemi.com . ? latticeecp/ec sysio usage guide (tn1056) ? isptracy internal logic analyzer guide (tn1054) ? latticeecp/ec sysclock pll design and usage guide (tn1049) ? memory usage guide for latticeecp/ec devices (tn1051) ? latticeecp/ec ddr usage guide (tn1050) ? estimating power using power calculator for latticeecp/ec devices (tn1052) ? sysdsp/mac usage guide (tn1057) ? latticeecp/ec sysconfig usage guide (tn1053) ? ieee 1149.1 boundary scan testability in lattice devices f or further information on interface standards refer to the following web sites: ? jedec standards (lvttl, lvcmos, sstl, hstl): www .jedec.org ? pci: ww .pcisig.com latticeecp/ec family data sheet supplemental information

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